1 //==========================================================================
5 // SoC [platform] specific RedBoot commands
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
42 #include <cyg/hal/hal_intr.h>
43 #include <cyg/hal/plf_mmap.h>
44 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #include <cyg/hal/hal_cache.h>
47 typedef unsigned long long u64;
48 typedef unsigned int u32;
49 typedef unsigned short u16;
50 typedef unsigned char u8;
52 #define SZ_DEC_1M 1000000
53 #define PLL_PD_MAX 16 //actual pd+1
54 #define PLL_MFI_MAX 15
55 #define PLL_MFI_MIN 6 // See TLSbo80174
56 #define PLL_MFD_MAX 1024 //actual mfd+1
57 #define PLL_MFN_MAX 1022
58 #define PLL_MFN_MAX_2 510
61 #define AHB_DIV_MAX 16
66 #define PLL_FREQ_MAX (2 * PLL_REF_CLK * PLL_MFI_MAX)
67 #define PLL_FREQ_MIN ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
68 #define AHB_CLK_MAX 133333333
69 #define IPG_CLK_MAX (AHB_CLK_MAX / 2)
70 #define NFC_CLK_MAX 33333333
72 #define ERR_WRONG_CLK -1
76 #define ERR_NO_PRESC -5
78 u32 pll_clock(enum plls pll);
79 u32 get_main_clock(enum main_clocks clk);
80 u32 get_peri_clock(enum peri_clocks clk);
82 static u32 pll_mfd_fixed;
84 static void clock_setup(int argc, char *argv[]);
85 static void clko(int argc, char *argv[]);
86 extern unsigned int g_clock_src;
87 extern unsigned int system_rev;
90 #define MXC_PERCLK_NUM 4
93 "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
94 "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]] \n\n\
95 If a divider is zero or no divider is specified, the optimal divider values \n\
96 will be chosen. Examples:\n\
97 [clock] -> Show various clocks\n\
98 [clock 266] -> Core=266 AHB=133 IPG=66.5\n\
99 [clock 350] -> Core=350 AHB=117 IPG=58.5\n\
100 [clock 266:4] -> Core=266 AHB=66.5(Core/4) IPG=66.5\n\
101 [clock 266:4:2] -> Core=266 AHB=66.5(Core/4) IPG=33.25(AHB/2)\n",
106 * This is to calculate various parameters based on reference clock and
107 * targeted clock based on the equation:
108 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
109 * This calculation is based on a fixed MFD value for simplicity.
111 * @param ref reference clock freq
112 * @param target targeted clock in HZ
113 * @param p_pd calculated pd value (pd value from register + 1) upon return
114 * @param p_mfi calculated actual mfi value upon return
115 * @param p_mfn calculated actual mfn value upon return
116 * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
118 * @return 0 if successful; non-zero otherwise.
120 int calc_pll_params(u32 ref, u32 target, u32 *p_pd,
121 u32 *p_mfi, u32 *p_mfn, u32 *p_mfd)
123 u64 pd, mfi, mfn, n_target = (u64)target, n_ref = (u64)ref;
125 if (g_clock_src == FREQ_26MHZ) {
126 pll_mfd_fixed = 26 * 16;
127 } else if (g_clock_src == FREQ_27MHZ) {
128 pll_mfd_fixed = 27 * 16;
133 // Make sure targeted freq is in the valid range. Otherwise the
134 // following calculation might be wrong!!!
135 if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
136 return ERR_WRONG_CLK;
138 // Use n_target and n_ref to avoid overflow
139 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
140 mfi = (n_target * pd) / (2 * n_ref);
141 if (mfi > PLL_MFI_MAX) {
143 } else if (mfi < PLL_MFI_MIN) {
148 // Now got pd and mfi already
149 mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
150 // Check mfn within limit and mfn < denominator
151 if (sys_ver == SOC_SILICONID_Rev1_0) {
152 if (mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
156 if (mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
161 if (pd > PLL_PD_MAX) {
167 *p_mfd = pll_mfd_fixed;
171 static u32 per_clk_old[MXC_PERCLK_NUM];
174 * This function assumes the expected core clock has to be changed by
175 * modifying the PLL. This is NOT true always but for most of the times,
176 * it is. So it assumes the PLL output freq is the same as the expected
177 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
178 * In the latter case, it will try to increase the presc value until
179 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
180 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
181 * on the targeted PLL and reference input clock to the PLL. Lastly,
182 * it sets the register based on these values along with the dividers.
183 * Note 1) There is no value checking for the passed-in divider values
184 * so the caller has to make sure those values are sensible.
185 * 2) Also adjust the NFC divider such that the NFC clock doesn't
186 * exceed NFC_CLK_MAX (which is 33MHz now).
187 * 3) Added feature to maintain the perclock before and after the call.
188 * !!!! 4) This function can't have printf in it since the serial i/f is
191 * @param ref pll input reference clock (32KHz or 26MHz)
192 * @param core_clk core clock in Hz
193 * @param ahb_div ahb divider to divide the core clock to get ahb clock
194 * (ahb_div - 1) needs to be set in the register
195 * @param ipg_div ipg divider to divide the ahb clock to get ipg clock
196 * (ipg_div - 1) needs to be set in the register
197 # @return 0 if successful; non-zero otherwise
199 int configure_clock(u32 ref, u32 core_clk, u32 ahb_div, u32 ipg_div)
201 u32 pll, presc = 1, pd, mfi, mfn, mfd, brmo = 1, cscr, mpctl0;
202 u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
203 u32 per_div[MXC_PERCLK_NUM];
204 int ret, i, arm_src = 0;
206 per_clk_old[0] = get_peri_clock(PER_CLK1);
207 per_clk_old[1] = get_peri_clock(PER_CLK2);
208 per_clk_old[2] = get_peri_clock(PER_CLK3);
209 per_clk_old[3] = get_peri_clock(PER_CLK4);
211 // assume pll default to core clock first
212 if (sys_ver == SOC_SILICONID_Rev1_0) {
216 if (core_clk > (266 * SZ_DEC_1M)) {
220 pll = core_clk * 3 / 2;
222 nfc_div_factor = ahb_div;
225 // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
226 // Otherwise, need to calculate presc value below and adjust the targeted pll
227 if (pll < PLL_FREQ_MIN) {
229 if(sys_ver == SOC_SILICONID_Rev1_0) {
230 presc_max = PRESC_MAX;
232 presc_max = ARM_DIV_MAX;
235 for (presc = 1; presc <= presc_max; presc++) {
236 if ((pll * presc) > PLL_FREQ_MIN) {
240 if (presc == (presc_max + 1)) {
241 diag_printf("can't make presc=%d\n", presc);
244 if (sys_ver == SOC_SILICONID_Rev1_0) {
245 pll = core_clk * presc;
247 pll = 3 * core_clk * presc / 2;
250 // pll is now the targeted pll output. Use it along with ref input clock
251 // to get pd, mfi, mfn, mfd
252 if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
253 #ifdef CMD_CLOCK_DEBUG
254 diag_printf("can't find pll parameters: %d\n", ret);
258 #ifdef CMD_CLOCK_DEBUG
259 diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
260 ref, pll, pd, mfi, mfn, mfd);
263 // blindly increase divider first to avoid too fast ahbclk and ipgclk
264 // in case the core clock increases too much
265 cscr = readl(SOC_CRM_CSCR);
266 if (sys_ver == SOC_SILICONID_Rev1_0) {
267 hdiv = (pll + AHB_CLK_MAX -1) / AHB_CLK_MAX;
268 cscr = (cscr & ~(0x0000FF00)) | ((hdiv - 1) << 9) | (1 << 8);
270 if (core_clk > (266 * SZ_DEC_1M)) {
271 hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
273 hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
275 cscr = (cscr & ~(0x0000FF00)) | ((hdiv - 1) << 8);
277 writel(cscr, SOC_CRM_CSCR);
279 // update PLL register
280 if ((mfd < (10 * mfn)) && ((10 * mfn) < (9 * mfd)))
283 writel(1 << 6, SOC_CRM_MPCTL1);
285 mpctl0 = readl(SOC_CRM_MPCTL0);
286 mpctl0 = (mpctl0 & 0xC000C000) |
292 writel(mpctl0, SOC_CRM_MPCTL0);
295 writel((cscr | (1 << 18)), SOC_CRM_CSCR);
296 // check the LF bit to insure lock
297 while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
298 // have to add some delay for new values to take effect
299 for (i = 0; i < 100000; i++);
301 // PLL locked already so use the new divider values
302 cscr = readl(SOC_CRM_CSCR);
305 if (sys_ver == SOC_SILICONID_Rev1_0) {
306 cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
308 cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
310 writel(cscr, SOC_CRM_CSCR);
312 // Make sure optimal NFC clock but less than NFC_CLK_MAX
313 for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
314 if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
318 pcdr0 = readl(SOC_CRM_PCDR0);
319 if(sys_ver == SOC_SILICONID_Rev1_0) {
320 writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
323 writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
327 if(sys_ver == SOC_SILICONID_Rev1_0) {
328 pll = pll_clock(MCU_PLL) + 500000;
330 if (core_clk > (266 * SZ_DEC_1M)) {
331 pll = pll_clock(MCU_PLL) + 500000;
333 pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
336 for (i = 0; i < MXC_PERCLK_NUM; i++) {
337 per_div[i] = (pll / per_clk_old[i]) - 1;
339 writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
340 (per_div[0]), SOC_CRM_PCDR1);
345 static void clock_setup(int argc, char *argv[])
347 u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
348 u32 presc_max, ahb_div_max, pll;
354 if (g_clock_src == FREQ_27MHZ) {
355 diag_printf("Error: clock setup is not supported for 27MHz source\n\n");
358 for (i = 0; i < 3; i++) {
359 if (!parse_num(argv[1], &temp, &argv[1], ":")) {
360 diag_printf("Error: Invalid parameter\n");
366 core_clk = data[0] * SZ_DEC_1M;
367 ahb_div = data[1]; // actual register field + 1
368 ipg_div = data[2]; // actual register field + 1
370 if(sys_ver == SOC_SILICONID_Rev1_0) {
371 presc_max = PRESC_MAX;
372 ahb_div_max = AHB_DIV_MAX;
374 ahb_clk_in = core_clk;
376 presc_max = ARM_DIV_MAX;
377 ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
378 if (core_clk > (266 * SZ_DEC_1M)) {
380 ahb_clk_in = core_clk * 2 / 3;
382 pll = 3 * core_clk / 2;
383 ahb_clk_in = core_clk;
388 if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
389 diag_printf("Targeted core clock should be within [%d - %d]\n",
390 PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
394 // find the ahb divider
395 if (ahb_div > ahb_div_max) {
396 diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
397 ahb_div, ahb_div_max);
401 // no AHBCLK divider specified
402 for (ahb_div = 1; ; ahb_div++) {
403 if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
408 if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
409 diag_printf("Can't make AHB=%d since max=%d\n",
410 core_clk / ahb_div, AHB_CLK_MAX);
414 // find the ipg divider
415 ahb_clk = ahb_clk_in / ahb_div;
416 if (ipg_div > IPG_DIV_MAX) {
417 diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
418 ipg_div, IPG_DIV_MAX);
422 ipg_div++; // At least =1
423 if (ahb_clk > IPG_CLK_MAX)
424 ipg_div++; // Make it =2
426 if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
427 diag_printf("Can't make IPG=%d since max=%d\n",
428 (ahb_clk / ipg_div), IPG_CLK_MAX);
431 ipg_clk = ahb_clk / ipg_div;
433 diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
434 core_clk, ahb_clk, ipg_clk);
436 // stop the serial to be ready to adjust the clock
437 hal_delay_us(100000);
438 cyg_hal_plf_serial_stop();
440 ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
441 // restart the serial driver
442 cyg_hal_plf_serial_init();
443 hal_delay_us(100000);
446 diag_printf("Failed to setup clock: %d\n", ret);
450 // check for new per clock settings and warn user if there is a change.
451 if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
452 diag_printf("New per_clk1 changed! Old freq is %d\n", per_clk_old[0]);
454 if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
455 diag_printf("New per_clk2 changed! Old freq is %d\n", per_clk_old[1]);
457 if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
458 diag_printf("New per_clk3 changed! Old freq is %d\n", per_clk_old[2]);
460 if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
461 diag_printf("New per_clk4 changed! Old freq is %d\n", per_clk_old[3]);
464 diag_printf("\n<<<New clock setting>>>\n");
466 // Now printing clocks
468 diag_printf("\nMPLL\t\tSPLL\n");
469 diag_printf("=========================\n");
470 diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
471 diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
472 diag_printf("========================================================================\n");
473 diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
474 get_main_clock(CPU_CLK),
475 get_main_clock(AHB_CLK),
476 get_main_clock(IPG_CLK),
477 get_main_clock(NFC_CLK),
478 get_main_clock(USB_CLK));
480 diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
481 diag_printf("===========================================");
482 diag_printf("=============\n");
484 diag_printf("%-16d%-16d%-16d%-16d\n\n",
485 get_peri_clock(PER_CLK1),
486 get_peri_clock(PER_CLK2),
487 get_peri_clock(PER_CLK3),
488 get_peri_clock(PER_CLK4));
490 diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
491 diag_printf("========================================================\n");
492 diag_printf("%-16d%-16d%-16d%-16d\n\n",
493 get_peri_clock(H264_BAUD),
494 get_peri_clock(MSHC_BAUD),
495 get_peri_clock(SSI1_BAUD),
496 get_peri_clock(SSI2_BAUD));
497 diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
501 * This function returns the PLL output value in Hz based on pll.
503 u32 pll_clock(enum plls pll)
505 u64 mfi, mfn, mfd, pdf, ref_clk, pll_out;
506 u64 reg = readl(pll);
508 if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
511 pdf = (reg >> 26) & 0xF;
512 mfd = (reg >> 16) & 0x3FF;
513 mfi = (reg >> 10) & 0xF;
514 mfi = (mfi <= 5) ? 5: mfi;
517 ref_clk = g_clock_src;
519 pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
526 * This function returns the main clock value in Hz.
528 u32 get_main_clock(enum main_clocks clk)
530 u32 presc, ahb_div, ipg_pdf, nfc_div;
531 u32 ret_val = 0, usb_div;
532 u32 cscr = readl(SOC_CRM_CSCR);
533 u32 pcdr0 = readl(SOC_CRM_PCDR0);
535 if (sys_ver == SOC_SILICONID_Rev1_0) {
536 presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
538 presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
543 if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
544 ret_val = pll_clock(MCU_PLL) / presc;
546 ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
550 if (sys_ver == SOC_SILICONID_Rev1_0) {
551 ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
552 ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
554 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
555 ret_val = 2*pll_clock(MCU_PLL) / (3*ahb_div);
559 if (sys_ver == SOC_SILICONID_Rev1_0) {
560 ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
561 ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
562 ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
564 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
565 ret_val = pll_clock(MCU_PLL) / (3*ahb_div);
569 if (sys_ver == SOC_SILICONID_Rev1_0) {
570 nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
572 ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
574 nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
575 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
576 ret_val = 2*pll_clock(MCU_PLL) / (3*ahb_div*nfc_div);
580 usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
581 ret_val = pll_clock(SER_PLL) / usb_div;
584 diag_printf("Unknown clock: %d\n", clk);
591 * This function returns the peripheral clock value in Hz.
593 u32 get_peri_clock(enum peri_clocks clk)
595 u32 ret_val = 0, div;
596 u32 pcdr0 = readl(SOC_CRM_PCDR0);
597 u32 pcdr1 = readl(SOC_CRM_PCDR1);
598 u32 cscr = readl(SOC_CRM_CSCR);
602 div = (pcdr1 & 0x3F) + 1;
603 if (sys_ver == SOC_SILICONID_Rev1_0) {
604 ret_val = pll_clock(MCU_PLL) / div;
606 ret_val = 2*pll_clock(MCU_PLL) / (3*div);
612 div = ((pcdr1 >> 8) & 0x3F) + 1;
613 if (sys_ver == SOC_SILICONID_Rev1_0) {
614 ret_val = pll_clock(MCU_PLL) / div;
616 ret_val = 2*pll_clock(MCU_PLL) / (3*div);
620 div = ((pcdr1 >> 16) & 0x3F) + 1;
621 if (sys_ver == SOC_SILICONID_Rev1_0) {
622 ret_val = pll_clock(MCU_PLL) / div;
624 ret_val = 2*pll_clock(MCU_PLL) / (3*div);
628 div = ((pcdr1 >> 24) & 0x3F) + 1;
629 if (sys_ver == SOC_SILICONID_Rev1_0) {
630 ret_val = pll_clock(MCU_PLL) / div;
632 ret_val = 2*pll_clock(MCU_PLL) / (3*div);
636 div = (pcdr0 >> 16) & 0x3F;
637 if (sys_ver == SOC_SILICONID_Rev1_0) {
644 if ((cscr & (1 << 22)) != 0) {
645 // This takes care of 0.5*SSIDIV[0] by x2
646 if (sys_ver == SOC_SILICONID_Rev1_0) {
647 ret_val = (2 * pll_clock(MCU_PLL)) / div;
649 ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
652 ret_val = (2 * pll_clock(SER_PLL)) / div;
656 div = (pcdr0 >> 26) & 0x3F;
657 if (sys_ver == SOC_SILICONID_Rev1_0) {
664 if ((cscr & (1 << 23)) != 0) {
665 if (sys_ver == SOC_SILICONID_Rev1_0) {
666 ret_val = (2 * pll_clock(MCU_PLL)) / div;
668 ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
671 ret_val = (2 * pll_clock(SER_PLL)) / div;
675 if (sys_ver == SOC_SILICONID_Rev1_0) {
676 div = (pcdr0 >> 8) & 0xF;
681 div = (pcdr0 >> 10) & 0x3F;
684 if ((cscr & (1 << 21)) != 0) {
685 if (sys_ver == SOC_SILICONID_Rev1_0) {
686 ret_val = (2 * pll_clock(MCU_PLL)) / div;
688 ret_val = (4 * pll_clock(MCU_PLL)) / (3*div);
691 ret_val = (2 * pll_clock(SER_PLL)) / div;
695 if ((cscr & (1 << 20)) != 0) {
696 if (sys_ver == SOC_SILICONID_Rev1_0) {
697 div = (pcdr0 & 0x1F) + 1;
698 ret_val = pll_clock(MCU_PLL) / div;
700 div = (pcdr0 & 0x3F) + 1;
701 ret_val = 2*pll_clock(MCU_PLL) / (3*div);
704 div = (pcdr0 & 0x1F) + 1;
705 ret_val = (2 * pll_clock(SER_PLL)) / div;
709 diag_printf("%s(): This clock: %d not supported yet \n",
718 "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
719 " The output clock is the actual clock source freq divided by 8. Default is FCLK\n\
720 Note that the module clock will be turned on for reading!\n\
721 <0> - display current clko selection \n\
724 <3> - CLK26M (may see nothing if 26MHz Crystal is not connected) \n\
725 <4> - MPLL Reference CLK \n\
726 <5> - SPLL Reference CLK \n\
731 <10> - IPG_CLK (PERCLK) \n\
736 <15> - SSI 1 Baud \n\
737 <16> - SSI 2 Baud \n\
741 <20> - CLK60M Always \n\
742 <21> - CLK32K Always \n\
748 static u8* clko_name[] ={
752 "CLK26M (may see nothing if 26MHz Crystal is not connected)",
753 "MPLL Reference CLK",
754 "SPLL Reference CLK",
775 #define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
777 static void clko(int argc,char *argv[])
779 u32 action = 0, ccsr;
781 if (!scan_opts(argc, argv, 1, 0, 0, &action,
782 OPTION_ARG_TYPE_NUM, "action"))
785 if (action >= CLKO_MAX_INDEX) {
786 diag_printf("%d is not supported\n\n", action);
790 ccsr = readl(SOC_CRM_CCSR);
793 ccsr = (ccsr & (~0x1F)) + action - 1;
794 writel(ccsr, SOC_CRM_CCSR);
795 diag_printf("Set clko to ");
798 ccsr = readl(SOC_CRM_CCSR);
799 diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
800 diag_printf("CCSR register[0x%x] = 0x%x\n", SOC_CRM_CCSR, ccsr);
803 extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
804 extern int flash_erase(void *addr, int len, void **err_addr);
806 void auto_flash_start(void)
810 int nor_update = 1; //todo: need to support NAND
811 u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
812 u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
813 u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
815 if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
820 // Erase area to be programmed
821 if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
822 diag_printf("BEADDEAD\n");
825 diag_printf("BEADBEEF\n");
827 if ((stat = flash_program((void *)dst, (void *)src, sz,
829 diag_printf("BEADFEEF\n");
832 diag_printf("BEADCEEF\n");
835 RedBoot_init(auto_flash_start, RedBoot_INIT_LAST);
837 #define IIM_ERR_SHIFT 8
838 #define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
839 #define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
841 static void fuse_op_start(void)
843 /* Do not generate interrupt */
844 writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
845 // clear the status bits and error bits
846 writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
847 writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
851 * The action should be either:
856 static int poll_fuse_op_done(int action)
861 if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
862 diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
866 /* Poll busy bit till it is NOT set */
867 while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
870 /* Test for successful write */
871 status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
872 error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
874 if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
876 diag_printf("Even though the operation seems successful...\n");
877 diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
878 (IIM_BASE_ADDR + IIM_ERR_OFF), error);
882 diag_printf("%s(%d) failed\n", __FUNCTION__, action);
883 diag_printf("status address=0x%x, value=0x%x\n",
884 (IIM_BASE_ADDR + IIM_STAT_OFF), status);
885 diag_printf("There are some error(s) at addr=0x%x: 0x%x\n",
886 (IIM_BASE_ADDR + IIM_ERR_OFF), error);
890 static void sense_fuse(int bank, int row, int bit)
893 int addr, addr_l, addr_h, reg_addr;
897 addr = ((bank << 11) | (row << 3) | (bit & 0x7));
898 /* Set IIM Program Upper Address */
899 addr_h = (addr >> 8) & 0x000000FF;
900 /* Set IIM Program Lower Address */
901 addr_l = (addr & 0x000000FF);
903 #ifdef IIM_FUSE_DEBUG
904 diag_printf("%s: addr_h=0x%x, addr_l=0x%x\n",
905 __FUNCTION__, addr_h, addr_l);
907 writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
908 writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
910 writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
911 if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
912 diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
913 __FUNCTION__, bank, row, bit);
915 reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
917 diag_printf("fuses at (bank:%d, row:%d) = 0x%x\n", bank, row, readl(reg_addr));
920 void do_fuse_read(int argc, char *argv[])
922 unsigned long bank, row;
925 diag_printf("Useage: fuse_read <bank> <row>\n");
927 } else if (argc == 3) {
928 if (!parse_num(argv[1], &bank, &argv[1], " ")) {
929 diag_printf("Error: Invalid parameter\n");
932 if (!parse_num(*(&argv[2]), &row, &argv[2], " ")) {
933 diag_printf("Error: Invalid parameter\n");
937 diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
938 sense_fuse(bank, row, 0);
941 diag_printf("Passing in wrong arguments: %d\n", argc);
942 diag_printf("Useage: fuse_read <bank> <row>\n");
946 /* Blow fuses based on the bank, row and bit positions (all 0-based)
948 static int fuse_blow(int bank,int row,int bit)
950 int addr, addr_l, addr_h, ret = -1;
954 /* Disable IIM Program Protect */
955 writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
957 addr = ((bank << 11) | (row << 3) | (bit & 0x7));
958 /* Set IIM Program Upper Address */
959 addr_h = (addr >> 8) & 0x000000FF;
960 /* Set IIM Program Lower Address */
961 addr_l = (addr & 0x000000FF);
963 #ifdef IIM_FUSE_DEBUG
964 diag_printf("blowing addr_h=0x%x, addr_l=0x%x\n", addr_h, addr_l);
967 writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
968 writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
969 /* Start Programming */
970 writel(0x31, IIM_BASE_ADDR + IIM_FCTL_OFF);
971 if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
975 /* Enable IIM Program Protect */
976 writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
981 * This command is added for burning IIM fuses
983 RedBoot_cmd("fuse_read",
989 RedBoot_cmd("fuse_blow",
991 "<bank> <row> <value>",
995 #define INIT_STRING "12345678"
996 static char ready_to_blow[] = INIT_STRING;
998 void quick_itoa(u32 num, char *a)
1001 for (i = 0; i <= 7; i++) {
1002 j = (num >> (4 * i)) & 0xF;
1003 k = (j < 10) ? '0' : ('a' - 0xa);
1008 void do_fuse_blow(int argc, char *argv[])
1010 unsigned long bank, row, value;
1014 diag_printf("It is too dangeous for you to use this command.\n");
1016 } else if (argc == 2) {
1017 if (strcasecmp(argv[1], "nandboot") == 0) {
1018 diag_printf("%s\n", "fuse blown not needed");
1021 } else if (argc == 3) {
1022 if (strcasecmp(argv[1], "nandboot") == 0) {
1023 #if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
1024 diag_printf("No need to blow any fuses for NAND boot on this platform\n\n");
1026 diag_printf("Ready to burn NAND boot fuses\n");
1027 if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
1028 diag_printf("NAND BOOT fuse blown failed miserably ...\n");
1030 diag_printf("NAND BOOT fuse blown successfully ...\n");
1033 diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
1036 } else if (argc == 4) {
1037 if (!parse_num(argv[1], &bank, &argv[1], " ")) {
1038 diag_printf("Error: Invalid parameter\n");
1041 if (!parse_num(argv[2], &row, &argv[2], " ")) {
1042 diag_printf("Error: Invalid parameter\n");
1045 if (!parse_num(argv[3], &value, &argv[3], " ")) {
1046 diag_printf("Error: Invalid parameter\n");
1050 diag_printf("Blowing fuse at bank:%ld row:%ld value:%ld\n",
1052 for (i = 0; i < 8; i++) {
1053 if (((value >> i) & 0x1) == 0) {
1056 if (fuse_blow(bank, row, i) != 0) {
1057 diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
1060 diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
1064 sense_fuse(bank, row, 0);
1067 diag_printf("Passing in wrong arguments: %d\n", argc);
1069 /* Reset to default string */
1070 strcpy(ready_to_blow, INIT_STRING);
1073 /* precondition: m>0 and n>0. Let g=gcd(m,n). */
1074 int gcd(int m, int n)
1078 if(n > m) {t = m; m = n; n = t;} /* swap */
1084 #define CLOCK_SRC_DETECT_MS 100
1085 #define CLOCK_IPG_DEFAULT 66500000
1086 #define CLOCK_SRC_DETECT_MARGIN 500000
1087 void mxc_show_clk_input(void)
1090 u32 c1, c2, diff, ipg_real, num = 0;
1091 u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
1097 diag_printf("FPM enabled --> 32KHz input source\n");
1102 diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
1106 // enable GPT with IPG clock input
1107 writel(0x241, GPT_BASE_ADDR + GPTCR);
1109 writel(0, GPT_BASE_ADDR + GPTPR);
1111 c1 = readl(GPT_BASE_ADDR + GPTCNT);
1112 // use 32KHz input clock to get the delay
1113 hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
1114 c2 = readl(GPT_BASE_ADDR + GPTCNT);
1115 diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
1117 ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
1119 if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
1120 if (g_clock_src != FREQ_27MHZ)
1122 } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
1123 if (g_clock_src != FREQ_26MHZ)
1127 diag_printf("Error: Actural clock input is %d MHz\n", num);
1128 diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
1129 ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
1130 diag_printf(" But clock source defined to be %d\n\n", g_clock_src);
1131 hal_delay_us(2000000);
1133 diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n\n",
1134 ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
1135 diag_printf("clock source defined to be %d\n\n", g_clock_src);
1140 RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
1142 void clock_spi_enable(unsigned int spi_clk)
1144 unsigned int reg = readl(SOC_CRM_PCCR1);
1147 writel(reg | (1 << 9), SOC_CRM_PCCR1);
1149 reg = readl(SOC_CRM_PCCR0);
1151 if (spi_clk == SPI1_CLK) {
1152 writel(reg | (1 << 31), SOC_CRM_PCCR0);
1153 gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
1154 gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
1155 gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
1156 gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
1157 gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
1158 gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
1159 gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
1160 } else if (spi_clk == SPI2_CLK) {
1161 writel(reg | (1 << 30), SOC_CRM_PCCR0);