1 //==========================================================================
5 // SoC [platform] specific RedBoot commands
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
42 #include <cyg/hal/hal_intr.h>
43 #include <cyg/hal/plf_mmap.h>
44 #include <cyg/hal/hal_soc.h> // Hardware definitions
45 #include <cyg/hal/hal_cache.h>
47 typedef unsigned long long u64;
48 typedef unsigned int u32;
49 typedef unsigned short u16;
50 typedef unsigned char u8;
52 #define SZ_DEC_1M 1000000
53 #define PLL_PD_MAX 16 //actual pd+1
54 #define PLL_MFI_MAX 15
55 #define PLL_MFI_MIN 6 // See TLSbo80174
56 #define PLL_MFD_MAX 1024 //actual mfd+1
57 #define PLL_MFN_MAX 1022
58 #define PLL_MFN_MAX_2 510
61 #define AHB_DIV_MAX 16
66 #define PLL_FREQ_MAX (2 * PLL_REF_CLK * PLL_MFI_MAX)
67 #define PLL_FREQ_MIN ((2 * PLL_REF_CLK * PLL_MFI_MIN) / PLL_PD_MAX)
68 #define AHB_CLK_MAX 133333333
69 #define IPG_CLK_MAX (AHB_CLK_MAX / 2)
70 #define NFC_CLK_MAX 33333333
72 #define ERR_WRONG_CLK -1
76 #define ERR_NO_PRESC -5
78 u32 pll_clock(enum plls pll);
79 u32 get_main_clock(enum main_clocks clk);
80 u32 get_peri_clock(enum peri_clocks clk);
82 static u32 pll_mfd_fixed;
84 static void clock_setup(int argc, char *argv[]);
85 static void clko(int argc, char *argv[]);
86 extern unsigned int g_clock_src;
87 extern unsigned int system_rev;
90 #define MXC_PERCLK_NUM 4
93 "Setup/Display clock (max AHB=133MHz, max IPG=66.5MHz)\nSyntax:",
94 "[<core clock in MHz> [:<AHB-to-core divider>[:<IPG-to-AHB divider>]]]\n\n"
95 "If a divider is zero or no divider is specified, the optimum divider values\n"
96 "will be chosen. Examples:\n"
97 " [clock] -> Show various clocks\n"
98 " [clock 266] -> Core=266 AHB=133 IPG=66.5\n"
99 " [clock 350] -> Core=350 AHB=117 IPG=58.5\n"
100 " [clock 266:4] -> Core=266 AHB=66.5(Core/4) IPG=66.5\n"
101 " [clock 266:4:2] -> Core=266 AHB=66.5(Core/4) IPG=33.25(AHB/2)\n",
106 * This is to calculate various parameters based on reference clock and
107 * targeted clock based on the equation:
108 * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
109 * This calculation is based on a fixed MFD value for simplicity.
111 * @param ref reference clock freq
112 * @param target targeted clock in HZ
113 * @param p_pd calculated pd value (pd value from register + 1) upon return
114 * @param p_mfi calculated actual mfi value upon return
115 * @param p_mfn calculated actual mfn value upon return
116 * @param p_mfd fixed mfd value (mfd value from register + 1) upon return
118 * @return 0 if successful; non-zero otherwise.
120 int calc_pll_params(u32 ref, u32 target, int *p_pd,
121 int *p_mfi, int *p_mfn, int *p_mfd)
124 u64 n_target = target, n_ref = ref;
126 if (g_clock_src == FREQ_26MHZ) {
127 pll_mfd_fixed = 26 * 16;
128 } else if (g_clock_src == FREQ_27MHZ) {
129 pll_mfd_fixed = 27 * 16;
134 // Make sure targeted freq is in the valid range. Otherwise the
135 // following calculation might be wrong!!!
136 if (target < PLL_FREQ_MIN || target > PLL_FREQ_MAX) {
137 return ERR_WRONG_CLK;
139 // Use n_target and n_ref to avoid overflow
140 for (pd = 1; pd <= PLL_PD_MAX; pd++) {
141 mfi = (n_target * pd) / (2 * n_ref);
142 if (mfi > PLL_MFI_MAX) {
144 } else if (mfi < PLL_MFI_MIN) {
149 // Now got pd and mfi already
150 mfn = (((n_target * pd) / 2 - n_ref * mfi) * pll_mfd_fixed) / n_ref;
151 // Check mfn within limit and mfn < denominator
152 if (sys_ver == SOC_SILICONID_Rev1_0) {
153 if (mfn < 0 || mfn > PLL_MFN_MAX || mfn >= pll_mfd_fixed) {
157 if (mfn < -PLL_MFN_MAX_2 || mfn > PLL_MFN_MAX_2 || mfn >= pll_mfd_fixed) {
162 if (pd > PLL_PD_MAX) {
168 *p_mfd = pll_mfd_fixed;
172 static u32 per_clk_old[MXC_PERCLK_NUM];
175 * This function assumes the expected core clock has to be changed by
176 * modifying the PLL. This is NOT true always but for most of the times,
177 * it is. So it assumes the PLL output freq is the same as the expected
178 * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN.
179 * In the latter case, it will try to increase the presc value until
180 * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to
181 * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based
182 * on the targeted PLL and reference input clock to the PLL. Lastly,
183 * it sets the register based on these values along with the dividers.
184 * Note 1) There is no value checking for the passed-in divider values
185 * so the caller has to make sure those values are sensible.
186 * 2) Also adjust the NFC divider such that the NFC clock doesn't
187 * exceed NFC_CLK_MAX (which is 33MHz now).
188 * 3) Added feature to maintain the perclock before and after the call.
189 * !!!! 4) This function can't have printf in it since the serial i/f is
192 * @param ref pll input reference clock (32KHz or 26MHz)
193 * @param core_clk core clock in Hz
194 * @param ahb_div ahb divider to divide the core clock to get ahb clock
195 * (ahb_div - 1) needs to be set in the register
196 * @param ipg_div ipg divider to divide the ahb clock to get ipg clock
197 * (ipg_div - 1) needs to be set in the register
198 # @return 0 if successful; non-zero otherwise
200 #define CMD_CLOCK_DEBUG
201 int configure_clock(u32 ref, u32 core_clk, u32 ahb_div, u32 ipg_div)
204 int pd, mfi, mfn, mfd;
206 u32 pcdr0, nfc_div, hdiv, nfc_div_factor;
207 u32 per_div[MXC_PERCLK_NUM];
208 int ret, i, arm_src = 0;
210 per_clk_old[0] = get_peri_clock(PER_CLK1);
211 per_clk_old[1] = get_peri_clock(PER_CLK2);
212 per_clk_old[2] = get_peri_clock(PER_CLK3);
213 per_clk_old[3] = get_peri_clock(PER_CLK4);
214 diag_printf("per1=%9u\n", per_clk_old[0]);
215 diag_printf("per2=%9u\n", per_clk_old[1]);
216 diag_printf("per3=%9u\n", per_clk_old[2]);
217 diag_printf("per4=%9u\n", per_clk_old[3]);
218 // assume pll default to core clock first
219 if (sys_ver == SOC_SILICONID_Rev1_0) {
223 if (core_clk > 266 * SZ_DEC_1M) {
227 pll = core_clk * 3 / 2;
229 nfc_div_factor = ahb_div;
232 // when core_clk >= PLL_FREQ_MIN, the presc can be 1.
233 // Otherwise, need to calculate presc value below and adjust the targeted pll
234 if (pll < PLL_FREQ_MIN) {
237 if (sys_ver == SOC_SILICONID_Rev1_0) {
238 presc_max = PRESC_MAX;
240 presc_max = ARM_DIV_MAX;
243 for (presc = 1; presc <= presc_max; presc++) {
244 if (pll * presc > PLL_FREQ_MIN) {
248 if (presc == presc_max + 1) {
249 diag_printf("can't make presc=%d\n", presc);
252 if (sys_ver == SOC_SILICONID_Rev1_0) {
253 pll = core_clk * presc;
255 pll = 3 * core_clk * presc / 2;
258 // pll is now the targeted pll output. Use it along with ref input clock
259 // to get pd, mfi, mfn, mfd
260 if ((ret = calc_pll_params(ref, pll, &pd, &mfi, &mfn, &mfd)) != 0) {
261 #ifdef CMD_CLOCK_DEBUG
262 diag_printf("can't find pll parameters: %d\n", ret);
266 #ifdef CMD_CLOCK_DEBUG
267 diag_printf("ref=%d, pll=%d, pd=%d, mfi=%d,mfn=%d, mfd=%d\n",
268 ref, pll, pd, mfi, mfn, mfd);
271 // blindly increase divider first to avoid too fast ahbclk and ipgclk
272 // in case the core clock increases too much
273 cscr = readl(SOC_CRM_CSCR);
274 if (sys_ver == SOC_SILICONID_Rev1_0) {
275 hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
276 cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 9) | (1 << 8);
278 if (core_clk > 266 * SZ_DEC_1M) {
279 hdiv = (pll + AHB_CLK_MAX - 1) / AHB_CLK_MAX;
281 hdiv = (2 * pll + 3 * AHB_CLK_MAX - 1) / (3 * AHB_CLK_MAX);
283 cscr = (cscr & ~0x0000FF00) | ((hdiv - 1) << 8);
285 writel(cscr, SOC_CRM_CSCR);
287 // update PLL register
288 if (!((mfd < 10 * mfn) && (10 * mfn < 9 * mfd)))
289 writel(1 << 6, SOC_CRM_MPCTL1);
291 mpctl0 = readl(SOC_CRM_MPCTL0);
292 mpctl0 = (mpctl0 & 0xC000C000) |
298 writel(mpctl0, SOC_CRM_MPCTL0);
301 writel((cscr | (1 << 18)), SOC_CRM_CSCR);
302 // check the LF bit to insure lock
303 while ((readl(SOC_CRM_MPCTL1) & (1 << 15)) == 0);
304 // have to add some delay for new values to take effect
305 for (i = 0; i < 100000; i++);
307 // PLL locked already so use the new divider values
308 cscr = readl(SOC_CRM_CSCR);
311 if (sys_ver == SOC_SILICONID_Rev1_0) {
312 cscr |= ((presc - 1) << 13) | ((ahb_div - 1) << 9) | ((ipg_div - 1) << 8);
314 cscr |= (arm_src << 15) | ((presc - 1) << 12) | ((ahb_div - 1) << 8);
316 writel(cscr, SOC_CRM_CSCR);
318 // Make sure optimal NFC clock but less than NFC_CLK_MAX
319 for (nfc_div = 1; nfc_div <= 16; nfc_div++) {
320 if ((core_clk / (nfc_div_factor * nfc_div)) <= NFC_CLK_MAX) {
324 pcdr0 = readl(SOC_CRM_PCDR0);
325 if (sys_ver == SOC_SILICONID_Rev1_0) {
326 writel(((pcdr0 & 0xFFFF0FFF) | ((nfc_div - 1) << 12)),
329 writel(((pcdr0 & 0xFFFFF3CF) | ((nfc_div - 1) << 6)),
333 if (sys_ver == SOC_SILICONID_Rev1_0) {
334 pll = pll_clock(MCU_PLL) + 500000;
336 if (core_clk > (266 * SZ_DEC_1M)) {
337 pll = pll_clock(MCU_PLL) + 500000;
339 pll = 2 * pll_clock(MCU_PLL) / 3 + 500000;
342 for (i = 0; i < MXC_PERCLK_NUM; i++) {
343 per_div[i] = (pll / per_clk_old[i]) - 1;
345 writel((per_div[3] << 24) | (per_div[2] << 16) | (per_div[1] << 8) |
346 (per_div[0]), SOC_CRM_PCDR1);
351 static void clock_setup(int argc, char *argv[])
353 u32 i, core_clk, ipg_div, data[3], ahb_div, ahb_clk, ahb_clk_in, ipg_clk;
354 u32 presc_max, ahb_div_max, pll;
360 if (g_clock_src == FREQ_27MHZ) {
361 diag_printf("Error: clock setup is not supported for 27MHz source\n");
364 for (i = 0; i < 3; i++) {
365 if (!parse_num(argv[1], &temp, &argv[1], ":")) {
366 diag_printf("Error: Invalid parameter\n");
372 core_clk = data[0] * SZ_DEC_1M;
373 ahb_div = data[1]; // actual register field + 1
374 ipg_div = data[2]; // actual register field + 1
376 if (sys_ver == SOC_SILICONID_Rev1_0) {
377 presc_max = PRESC_MAX;
378 ahb_div_max = AHB_DIV_MAX;
380 ahb_clk_in = core_clk;
382 presc_max = ARM_DIV_MAX;
383 ahb_div_max = AHB_DIV_MAX / ARM_DIV_MAX;
384 if (core_clk > (266 * SZ_DEC_1M)) {
386 ahb_clk_in = core_clk * 2 / 3;
388 pll = 3 * core_clk / 2;
389 ahb_clk_in = core_clk;
394 if (pll < (PLL_FREQ_MIN / presc_max) || pll > PLL_FREQ_MAX) {
395 diag_printf("Targeted core clock should be within [%d - %d]\n",
396 PLL_FREQ_MIN / presc_max, PLL_FREQ_MAX);
400 // find the ahb divider
401 if (ahb_div > ahb_div_max) {
402 diag_printf("Invalid AHB divider: %d. Maximum value is %d\n",
403 ahb_div, ahb_div_max);
407 // no AHBCLK divider specified
408 for (ahb_div = 1; ; ahb_div++) {
409 if ((ahb_clk_in / ahb_div) <= AHB_CLK_MAX) {
414 if (ahb_div > ahb_div_max || (ahb_clk_in / ahb_div) > AHB_CLK_MAX) {
415 diag_printf("Can't make AHB=%d since max=%d\n",
416 core_clk / ahb_div, AHB_CLK_MAX);
420 // find the ipg divider
421 ahb_clk = ahb_clk_in / ahb_div;
422 if (ipg_div > IPG_DIV_MAX) {
423 diag_printf("Invalid IPG divider: %d. Maximum value is %d\n",
424 ipg_div, IPG_DIV_MAX);
428 ipg_div++; // At least =1
429 if (ahb_clk > IPG_CLK_MAX)
430 ipg_div++; // Make it =2
432 if (ipg_div > IPG_DIV_MAX || (ahb_clk / ipg_div) > IPG_CLK_MAX) {
433 diag_printf("Can't make IPG=%d since max=%d\n",
434 (ahb_clk / ipg_div), IPG_CLK_MAX);
437 ipg_clk = ahb_clk / ipg_div;
439 diag_printf("Trying to set core=%d ahb=%d ipg=%d...\n",
440 core_clk, ahb_clk, ipg_clk);
442 // stop the serial to be ready to adjust the clock
443 hal_delay_us(100000);
444 cyg_hal_plf_serial_stop();
446 ret = configure_clock(PLL_REF_CLK, core_clk, ahb_div, ipg_div);
447 // restart the serial driver
448 cyg_hal_plf_serial_init();
449 hal_delay_us(100000);
452 diag_printf("Failed to setup clock: %d\n", ret);
456 // check for new per clock settings and warn user if there is a change.
457 if (per_clk_old[0] != get_peri_clock(PER_CLK1)) {
458 diag_printf("per_clk1 changed; old clock was: %u\n", per_clk_old[0]);
460 if (per_clk_old[1] != get_peri_clock(PER_CLK2)) {
461 diag_printf("per_clk2 changed; old clock was: %u\n", per_clk_old[1]);
463 if (per_clk_old[2] != get_peri_clock(PER_CLK3)) {
464 diag_printf("per_clk3 changed; old clock was: %u\n", per_clk_old[2]);
466 if (per_clk_old[3] != get_peri_clock(PER_CLK4)) {
467 diag_printf("per_clk4 changed; old clock was: %u\n", per_clk_old[3]);
470 diag_printf("\n<<<New clock setting>>>\n");
472 // Now printing clocks
474 diag_printf("\nMPLL\t\tSPLL\n");
475 diag_printf("=========================\n");
476 diag_printf("%-16d%-16d\n\n", pll_clock(MCU_PLL), pll_clock(SER_PLL));
477 diag_printf("CPU\t\tAHB\t\tIPG\t\tNFC\t\tUSB\n");
478 diag_printf("========================================================================\n");
479 diag_printf("%-16d%-16d%-16d%-16d%-16d\n\n",
480 get_main_clock(CPU_CLK),
481 get_main_clock(AHB_CLK),
482 get_main_clock(IPG_CLK),
483 get_main_clock(NFC_CLK),
484 get_main_clock(USB_CLK));
486 diag_printf("PER1\t\tPER2\t\tPER3\t\tPER4\n");
487 diag_printf("===========================================");
488 diag_printf("=============\n");
490 diag_printf("%-16d%-16d%-16d%-16d\n\n",
491 get_peri_clock(PER_CLK1),
492 get_peri_clock(PER_CLK2),
493 get_peri_clock(PER_CLK3),
494 get_peri_clock(PER_CLK4));
496 diag_printf("H264\t\tMSHC\t\tSSI1\t\tSSI2\n");
497 diag_printf("========================================================\n");
498 diag_printf("%-16d%-16d%-16d%-16d\n\n",
499 get_peri_clock(H264_BAUD),
500 get_peri_clock(MSHC_BAUD),
501 get_peri_clock(SSI1_BAUD),
502 get_peri_clock(SSI2_BAUD));
503 diag_printf("PERCLK: 1-<UART|GPT|PWM> 2-<SDHC|CSPI> 3-<LCDC> 4-<CSI>\n");
507 * This function returns the PLL output value in Hz based on pll.
509 u32 pll_clock(enum plls pll)
511 int mfi, mfn, mfd, pdf;
513 u32 reg = readl(pll);
516 if ((pll == SER_PLL) && (sys_ver == SOC_SILICONID_Rev2_0)) {
519 pdf = (reg >> 26) & 0xF;
520 mfd = (reg >> 16) & 0x3FF;
521 mfi = (reg >> 10) & 0xF;
529 ref_clk = g_clock_src;
531 pll_out = (2 * ref_clk * mfi + ((2 * ref_clk * mfn) / (mfd + 1))) /
538 * This function returns the main clock value in Hz.
540 u32 get_main_clock(enum main_clocks clk)
542 u32 presc, ahb_div, ipg_pdf, nfc_div;
543 u32 ret_val = 0, usb_div;
544 u32 cscr = readl(SOC_CRM_CSCR);
545 u32 pcdr0 = readl(SOC_CRM_PCDR0);
547 if (sys_ver == SOC_SILICONID_Rev1_0) {
548 presc = ((cscr >> CRM_CSCR_PRESC_OFFSET) & 0x7) + 1;
550 presc = ((cscr >> CRM_CSCR_ARM_OFFSET) & 0x3) + 1;
555 if ((sys_ver == SOC_SILICONID_Rev1_0) || (cscr & CRM_CSCR_ARM_SRC)) {
556 ret_val = pll_clock(MCU_PLL) / presc;
558 ret_val = 2 * pll_clock(MCU_PLL) / (3 * presc);
562 if (sys_ver == SOC_SILICONID_Rev1_0) {
563 ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
564 ret_val = pll_clock(MCU_PLL) / (presc * ahb_div);
566 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
567 ret_val = 2 * pll_clock(MCU_PLL) / (3 * ahb_div);
571 if (sys_ver == SOC_SILICONID_Rev1_0) {
572 ahb_div = ((cscr >> CRM_CSCR_BCLKDIV_OFFSET) & 0xF) + 1;
573 ipg_pdf = ((cscr >> CRM_CSCR_IPDIV_OFFSET) & 0x1) + 1;
574 ret_val = pll_clock(MCU_PLL) / (presc * ahb_div * ipg_pdf);
576 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
577 ret_val = pll_clock(MCU_PLL) / (3 * ahb_div);
581 if (sys_ver == SOC_SILICONID_Rev1_0) {
582 nfc_div = ((pcdr0 >> 12) & 0xF) + 1;
584 ret_val = pll_clock(MCU_PLL) / (presc * nfc_div);
586 nfc_div = ((pcdr0 >> 6) & 0xF) + 1;
587 ahb_div = ((cscr >> CRM_CSCR_AHB_OFFSET) & 0x3) + 1;
588 ret_val = 2*pll_clock(MCU_PLL) / (3 * ahb_div * nfc_div);
592 usb_div = ((cscr >> CRM_CSCR_USB_DIV_OFFSET) & 0x7) + 1;
593 ret_val = pll_clock(SER_PLL) / usb_div;
596 diag_printf("Unknown clock: %d\n", clk);
603 * This function returns the peripheral clock value in Hz.
605 u32 get_peri_clock(enum peri_clocks clk)
607 u32 ret_val = 0, div;
608 u32 pcdr0 = readl(SOC_CRM_PCDR0);
609 u32 pcdr1 = readl(SOC_CRM_PCDR1);
610 u32 cscr = readl(SOC_CRM_CSCR);
614 div = (pcdr1 & 0x3F) + 1;
615 if (sys_ver == SOC_SILICONID_Rev1_0) {
616 ret_val = pll_clock(MCU_PLL) / div;
618 ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
624 div = ((pcdr1 >> 8) & 0x3F) + 1;
625 if (sys_ver == SOC_SILICONID_Rev1_0) {
626 ret_val = pll_clock(MCU_PLL) / div;
628 ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
632 div = ((pcdr1 >> 16) & 0x3F) + 1;
633 if (sys_ver == SOC_SILICONID_Rev1_0) {
634 ret_val = pll_clock(MCU_PLL) / div;
636 ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
640 div = ((pcdr1 >> 24) & 0x3F) + 1;
641 if (sys_ver == SOC_SILICONID_Rev1_0) {
642 ret_val = pll_clock(MCU_PLL) / div;
644 ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
648 div = (pcdr0 >> 16) & 0x3F;
649 if (sys_ver == SOC_SILICONID_Rev1_0) {
656 if ((cscr & (1 << 22)) != 0) {
657 // This takes care of 0.5*SSIDIV[0] by x2
658 if (sys_ver == SOC_SILICONID_Rev1_0) {
659 ret_val = (2 * pll_clock(MCU_PLL)) / div;
661 ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
664 ret_val = (2 * pll_clock(SER_PLL)) / div;
668 div = (pcdr0 >> 26) & 0x3F;
669 if (sys_ver == SOC_SILICONID_Rev1_0) {
676 if ((cscr & (1 << 23)) != 0) {
677 if (sys_ver == SOC_SILICONID_Rev1_0) {
678 ret_val = (2 * pll_clock(MCU_PLL)) / div;
680 ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
683 ret_val = (2 * pll_clock(SER_PLL)) / div;
687 if (sys_ver == SOC_SILICONID_Rev1_0) {
688 div = (pcdr0 >> 8) & 0xF;
693 div = (pcdr0 >> 10) & 0x3F;
696 if ((cscr & (1 << 21)) != 0) {
697 if (sys_ver == SOC_SILICONID_Rev1_0) {
698 ret_val = (2 * pll_clock(MCU_PLL)) / div;
700 ret_val = (4 * pll_clock(MCU_PLL)) / (3 * div);
703 ret_val = (2 * pll_clock(SER_PLL)) / div;
707 if ((cscr & (1 << 20)) != 0) {
708 if (sys_ver == SOC_SILICONID_Rev1_0) {
709 div = (pcdr0 & 0x1F) + 1;
710 ret_val = pll_clock(MCU_PLL) / div;
712 div = (pcdr0 & 0x3F) + 1;
713 ret_val = 2 * pll_clock(MCU_PLL) / (3 * div);
716 div = (pcdr0 & 0x1F) + 1;
717 ret_val = (2 * pll_clock(SER_PLL)) / div;
721 diag_printf("%s(): This clock: %d not supported yet\n",
730 "Select clock source for CLKO (TP1 on EVB or S3 Pin 1)",
731 " The output clock is the actual clock source freq divided by 8. Default is FCLK\n"
732 " Note that the module clock will be turned on for reading!\n"
733 " <0> - display current clko selection\n"
736 " <3> - CLK26M (may see nothing if 26MHz Crystal is not connected)\n"
737 " <4> - MPLL Reference CLK\n"
738 " <5> - SPLL Reference CLK\n"
743 " <10> - IPG_CLK (PERCLK)\n"
748 " <15> - SSI 1 Baud\n"
749 " <16> - SSI 2 Baud\n"
751 " <18> - MSHC Baud\n"
752 " <19> - H264 Baud\n"
753 " <20> - CLK60M Always\n"
754 " <21> - CLK32K Always\n"
760 static u8* clko_name[] = {
764 "CLK26M (may see nothing if 26MHz Crystal is not connected)",
765 "MPLL Reference CLK",
766 "SPLL Reference CLK",
787 #define CLKO_MAX_INDEX (sizeof(clko_name) / sizeof(u8*))
789 static void clko(int argc,char *argv[])
791 u32 action = 0, ccsr;
793 if (!scan_opts(argc, argv, 1, 0, 0, &action,
794 OPTION_ARG_TYPE_NUM, "action"))
797 if (action >= CLKO_MAX_INDEX) {
798 diag_printf("%d is not supported\n", action);
802 ccsr = readl(SOC_CRM_CCSR);
805 ccsr = (ccsr & (~0x1F)) + action - 1;
806 writel(ccsr, SOC_CRM_CCSR);
807 diag_printf("Set clko to ");
810 ccsr = readl(SOC_CRM_CCSR);
811 diag_printf("%s\n", clko_name[(ccsr & 0x1F) + 1]);
812 diag_printf("CCSR register[0x%08lx] = 0x%08x\n", SOC_CRM_CCSR, ccsr);
815 extern int flash_program(void *_addr, void *_data, int len, void **err_addr);
816 extern int flash_erase(void *addr, int len, void **err_addr);
818 void auto_flash_start(void)
822 int nor_update = 1; //todo: need to support NAND
823 u32 src = readl(SERIAL_DOWNLOAD_SRC_REG);
824 u32 dst = readl(SERIAL_DOWNLOAD_TGT_REG);
825 u32 sz = readl(SERIAL_DOWNLOAD_SZ_REG);
827 if (readl(SERIAL_DOWNLOAD_MAGIC_REG) != SERIAL_DOWNLOAD_MAGIC) {
832 // Erase area to be programmed
833 if ((stat = flash_erase((void *)dst, sz, &err_addr)) != 0) {
834 diag_printf("BEADDEAD\n");
837 diag_printf("BEADBEEF\n");
839 if ((stat = flash_program((void *)dst, (void *)src, sz,
841 diag_printf("BEADFEEF\n");
844 diag_printf("BEADCEEF\n");
847 RedBoot_init(auto_flash_start, RedBoot_INIT_LAST);
849 #define IIM_ERR_SHIFT 8
850 #define POLL_FUSE_PRGD (IIM_STAT_PRGD | (IIM_ERR_PRGE << IIM_ERR_SHIFT))
851 #define POLL_FUSE_SNSD (IIM_STAT_SNSD | (IIM_ERR_SNSE << IIM_ERR_SHIFT))
853 static void fuse_op_start(void)
855 /* Do not generate interrupt */
856 writel(0, IIM_BASE_ADDR + IIM_STATM_OFF);
857 // clear the status bits and error bits
858 writel(0x3, IIM_BASE_ADDR + IIM_STAT_OFF);
859 writel(0xFE, IIM_BASE_ADDR + IIM_ERR_OFF);
863 * The action should be either:
868 static int poll_fuse_op_done(int action)
872 if (action != POLL_FUSE_PRGD && action != POLL_FUSE_SNSD) {
873 diag_printf("%s(%d) invalid operation\n", __FUNCTION__, action);
877 /* Poll busy bit till it is NOT set */
878 while ((readl(IIM_BASE_ADDR + IIM_STAT_OFF) & IIM_STAT_BUSY) != 0 ) {
881 /* Test for successful write */
882 status = readl(IIM_BASE_ADDR + IIM_STAT_OFF);
883 error = readl(IIM_BASE_ADDR + IIM_ERR_OFF);
885 if ((status & action) != 0 && (error & (action >> IIM_ERR_SHIFT)) == 0) {
887 diag_printf("Even though the operation seems successful...\n");
888 diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
889 (IIM_BASE_ADDR + IIM_ERR_OFF), error);
893 diag_printf("%s(%d) failed\n", __FUNCTION__, action);
894 diag_printf("status address=0x%08lx, value=0x%08x\n",
895 (IIM_BASE_ADDR + IIM_STAT_OFF), status);
896 diag_printf("There are some error(s) at addr=0x%08lx: 0x%08x\n",
897 (IIM_BASE_ADDR + IIM_ERR_OFF), error);
901 static void sense_fuse(int bank, int row, int bit)
904 int addr, addr_l, addr_h, reg_addr;
908 addr = ((bank << 11) | (row << 3) | (bit & 0x7));
909 /* Set IIM Program Upper Address */
910 addr_h = (addr >> 8) & 0x000000FF;
911 /* Set IIM Program Lower Address */
912 addr_l = (addr & 0x000000FF);
914 #ifdef IIM_FUSE_DEBUG
915 diag_printf("%s: addr_h=0x%02x, addr_l=0x%02x\n",
916 __FUNCTION__, addr_h, addr_l);
918 writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
919 writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
921 writel(0x8, IIM_BASE_ADDR + IIM_FCTL_OFF);
922 if ((ret = poll_fuse_op_done(POLL_FUSE_SNSD)) != 0) {
923 diag_printf("%s(bank: %d, row: %d, bit: %d failed\n",
924 __FUNCTION__, bank, row, bit);
926 reg_addr = IIM_BASE_ADDR + IIM_SDAT_OFF;
928 diag_printf("fuses at (bank:%d, row:%d) = 0x%02x\n", bank, row, readl(reg_addr));
931 void do_fuse_read(int argc, char *argv[])
933 unsigned long bank, row;
936 diag_printf("Usage: fuse_read <bank> <row>\n");
938 } else if (argc == 3) {
939 if (!parse_num(argv[1], &bank, &argv[1], " ")) {
940 diag_printf("Error: Invalid parameter\n");
943 if (!parse_num(argv[2], &row, &argv[2], " ")) {
944 diag_printf("Error: Invalid parameter\n");
948 diag_printf("Read fuse at bank:%ld row:%ld\n", bank, row);
949 sense_fuse(bank, row, 0);
952 diag_printf("Passing in wrong arguments: %d\n", argc);
953 diag_printf("Usage: fuse_read <bank> <row>\n");
957 /* Blow fuses based on the bank, row and bit positions (all 0-based)
959 int fuse_blow(int bank, int row, int bit)
961 int addr, addr_l, addr_h, ret = -1;
965 /* Disable IIM Program Protect */
966 writel(0xAA, IIM_BASE_ADDR + IIM_PREG_P_OFF);
968 addr = ((bank << 11) | (row << 3) | (bit & 0x7));
969 /* Set IIM Program Upper Address */
970 addr_h = (addr >> 8) & 0x000000FF;
971 /* Set IIM Program Lower Address */
972 addr_l = (addr & 0x000000FF);
974 diag_printf("blowing fuse bank %d row %d bit %d\n", bank, row, bit & 7);
975 #ifdef IIM_FUSE_DEBUG
976 diag_printf("blowing addr_h=0x%02x, addr_l=0x%02x\n", addr_h, addr_l);
979 writel(addr_h, IIM_BASE_ADDR + IIM_UA_OFF);
980 writel(addr_l, IIM_BASE_ADDR + IIM_LA_OFF);
981 /* Start Programming */
982 writel(0x71, IIM_BASE_ADDR + IIM_FCTL_OFF);
983 if (poll_fuse_op_done(POLL_FUSE_PRGD) == 0) {
987 /* Enable IIM Program Protect */
988 writel(0x0, IIM_BASE_ADDR + IIM_PREG_P_OFF);
993 * This command is added for burning IIM fuses
995 RedBoot_cmd("fuse_read",
1001 RedBoot_cmd("fuse_blow",
1003 "<bank> <row> <value>",
1007 #define INIT_STRING "12345678"
1008 static char ready_to_blow[] = INIT_STRING;
1010 void do_fuse_blow(int argc, char *argv[])
1012 unsigned long bank, row, value;
1016 diag_printf("It is too dangeous for you to use this command.\n");
1018 } else if (argc == 2) {
1019 if (strcasecmp(argv[1], "nandboot") == 0) {
1020 diag_printf("%s\n", "fuse blown not needed");
1023 } else if (argc == 3) {
1024 if (strcasecmp(argv[1], "nandboot") == 0) {
1025 #if defined(CYGPKG_HAL_ARM_MXC91131) || defined(CYGPKG_HAL_ARM_MX21) || defined(CYGPKG_HAL_ARM_MX27) || defined(CYGPKG_HAL_ARM_MX31)
1026 diag_printf("No need to blow any fuses for NAND boot on this platform\n");
1028 diag_printf("Ready to burn NAND boot fuses\n");
1029 if (fuse_blow(0, 16, 1) != 0 || fuse_blow(0, 16, 7) != 0) {
1030 diag_printf("NAND BOOT fuse blown failed miserably ...\n");
1032 diag_printf("NAND BOOT fuse blown successfully ...\n");
1035 diag_printf("Not ready: %s, %s\n", argv[1], argv[2]);
1038 } else if (argc == 4) {
1039 if (!parse_num(argv[1], &bank, &argv[1], " ")) {
1040 diag_printf("Error: Invalid fuse bank\n");
1043 if (!parse_num(argv[2], &row, &argv[2], " ")) {
1044 diag_printf("Error: Invalid fuse row\n");
1047 if (!parse_num(argv[3], &value, &argv[3], " ")) {
1048 diag_printf("Error: Invalid value\n");
1052 if (!verify_action("Confirm to blow fuse at bank:%ld row:%ld value:0x%02lx (%ld)",
1053 bank, row, value)) {
1054 diag_printf("fuse_blow canceled\n");
1058 for (i = 0; i < 8; i++) {
1059 if (((value >> i) & 0x1) == 0) {
1062 if (fuse_blow(bank, row, i) != 0) {
1063 diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d failed\n",
1066 diag_printf("fuse_blow(bank: %ld, row: %ld, bit: %d successful\n",
1070 sense_fuse(bank, row, 0);
1072 diag_printf("Passing in wrong arguments: %d\n", argc);
1074 /* Reset to default string */
1075 strcpy(ready_to_blow, INIT_STRING);
1078 /* precondition: m>0 and n>0. Let g=gcd(m,n). */
1079 int gcd(int m, int n)
1083 if (n > m) {t = m; m = n; n = t;} /* swap */
1089 #define CLOCK_SRC_DETECT_MS 100
1090 #define CLOCK_IPG_DEFAULT 66500000
1091 #define CLOCK_SRC_DETECT_MARGIN 500000
1092 void mxc_show_clk_input(void)
1095 u32 c1, c2, diff, ipg_real, num = 0;
1096 u32 prcs = (readl(CCM_BASE_ADDR + CLKCTL_CCMR) >> 1) & 0x3;
1102 diag_printf("FPM enabled --> 32KHz input source\n");
1107 diag_printf("Error %d: unknown clock source %d\n", __LINE__, prcs);
1111 // enable GPT with IPG clock input
1112 writel(0x241, GPT_BASE_ADDR + GPTCR);
1114 writel(0, GPT_BASE_ADDR + GPTPR);
1116 c1 = readl(GPT_BASE_ADDR + GPTCNT);
1117 // use 32KHz input clock to get the delay
1118 hal_delay_us(CLOCK_SRC_DETECT_MS * 1000);
1119 c2 = readl(GPT_BASE_ADDR + GPTCNT);
1120 diff = (c2 > c1) ? (c2 - c1) : (0xFFFFFFFF - c1 + c2);
1122 ipg_real = diff * (1000 / CLOCK_SRC_DETECT_MS);
1124 if (ipg_real > (CLOCK_IPG_DEFAULT + CLOCK_SRC_DETECT_MARGIN)) {
1125 if (g_clock_src != FREQ_27MHZ)
1127 } else if (ipg_real < (CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN)) {
1128 if (g_clock_src != FREQ_26MHZ)
1132 diag_printf("Error: Actual clock input is %d MHz\n", num);
1133 diag_printf(" ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
1134 ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
1135 diag_printf(" But clock source defined to be %d\n", g_clock_src);
1136 hal_delay_us(2000000);
1138 diag_printf("ipg_real=%d CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN=%d\n",
1139 ipg_real, CLOCK_IPG_DEFAULT - CLOCK_SRC_DETECT_MARGIN);
1140 diag_printf("clock source defined to be %d\n", g_clock_src);
1145 RedBoot_init(mxc_show_clk_input, RedBoot_INIT_LAST);
1147 void clock_spi_enable(unsigned int spi_clk)
1149 unsigned int reg = readl(SOC_CRM_PCCR1);
1152 writel(reg | (1 << 9), SOC_CRM_PCCR1);
1154 reg = readl(SOC_CRM_PCCR0);
1156 if (spi_clk == SPI1_CLK) {
1157 writel(reg | (1 << 31), SOC_CRM_PCCR0);
1158 gpio_request_mux(MX27_PIN_CSPI1_MOSI, GPIO_MUX_PRIMARY);
1159 gpio_request_mux(MX27_PIN_CSPI1_MISO, GPIO_MUX_PRIMARY);
1160 gpio_request_mux(MX27_PIN_CSPI1_SCLK, GPIO_MUX_PRIMARY);
1161 gpio_request_mux(MX27_PIN_CSPI1_RDY, GPIO_MUX_PRIMARY);
1162 gpio_request_mux(MX27_PIN_CSPI1_SS0, GPIO_MUX_PRIMARY);
1163 gpio_request_mux(MX27_PIN_CSPI1_SS1, GPIO_MUX_PRIMARY);
1164 gpio_request_mux(MX27_PIN_CSPI1_SS2, GPIO_MUX_PRIMARY);
1165 } else if (spi_clk == SPI2_CLK) {
1166 writel(reg | (1 << 30), SOC_CRM_PCCR0);