1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
43 #include <pkgconf/hal.h>
44 #include <pkgconf/system.h>
45 #include CYGBLD_HAL_PLATFORM_H
47 #include <cyg/infra/cyg_type.h> // base types
48 #include <cyg/infra/cyg_trac.h> // tracing macros
49 #include <cyg/infra/cyg_ass.h> // assertion macros
51 #include <cyg/hal/hal_misc.h> // Size constants
52 #include <cyg/hal/hal_io.h> // IO macros
53 #include <cyg/hal/hal_arch.h> // Register state info
54 #include <cyg/hal/hal_diag.h>
55 #include <cyg/hal/hal_intr.h> // Interrupt names
56 #include <cyg/hal/hal_cache.h> // Cache control
57 #include <cyg/hal/hal_soc.h> // Hardware definitions
58 #include <cyg/hal/hal_mm.h> // MMap table definitions
60 #include <cyg/infra/diag.h> // diag_printf
62 // Most initialization has already been done before we get here.
63 // All we do here is set up the interrupt environment.
64 // FIXME: some of the stuff in hal_platform_setup could be moved here.
66 externC void plf_hardware_init(void);
68 #define IIM_PROD_REV_SH 3
69 #define IIM_PROD_REV_LEN 5
70 #define IIM_SREV_REV_SH 4
71 #define IIM_SREV_REV_LEN 4
72 #define PROD_SIGNATURE_MX31 0x1
73 #define PROD_SIGNATURE_MX32 0x2
75 #define PROD_SIGNATURE_SUPPORTED_1 PROD_SIGNATURE_MX31
76 #define PROD_SIGNATURE_SUPPORTED_2 PROD_SIGNATURE_MX32
77 #define CHIP_VERSION_NONE 0xFFFFFFFF // invalid product ID
78 #define CHIP_VERSION_UNKNOWN 0xDEADBEEF // invalid chip rev
80 #define PART_NUMBER_OFFSET (12)
81 #define MAJOR_NUMBER_OFFSET (4)
82 #define MINOR_NUMBER_OFFSET (0)
85 * System_rev will have the following format
86 * 31-12 = part # (0x31, 0x32, 0x27, 0x91131, 0x91321, etc)
91 unsigned int system_rev = CHIP_REV_1_0;
92 static int find_correct_chip;
94 char HAL_PLATFORM_EXTRA[55] = "MX31 ADS (Freescale i.MX31 based) PASS 1.0 [x32 DDR]";
97 * This functions reads the IIM module and returns the system revision number.
98 * It returns the IIM silicon revision reg value if valid product rev is found.
99 . Otherwise, it returns -1.
101 static int read_system_rev(void)
105 val = readl(IIM_BASE_ADDR + IIM_PREV_OFF);
107 /* If the IIM doesn't contain valid product signature, return
108 * the lowest revision number */
109 if ((MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
110 PROD_SIGNATURE_SUPPORTED_1) &&
111 (MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) !=
112 PROD_SIGNATURE_SUPPORTED_2)){
113 return CHIP_VERSION_NONE;
116 /* Check if this is MX32 chip */
117 if (MXC_GET_FIELD(val, IIM_PROD_REV_LEN, IIM_PROD_REV_SH) ==
118 PROD_SIGNATURE_MX32) {
119 system_rev = 0x32 << PART_NUMBER_OFFSET; /* For MX32 Platform*/
120 HAL_PLATFORM_EXTRA[3] = '2';
121 HAL_PLATFORM_EXTRA[25] = '2';
123 system_rev = 0x31 << PART_NUMBER_OFFSET; /* For MX31 Platform*/
126 /* Now trying to retrieve the silicon rev from IIM's SREV register */
127 return readl(IIM_BASE_ADDR + IIM_SREV_OFF);
130 extern nfc_setup_func_t *nfc_setup;
131 unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz,
132 unsigned int is_mlc);
133 void hal_hardware_init(void)
135 volatile unsigned int esdmisc = readl(ESDCTL_BASE + 0x10);
136 volatile unsigned int esdctl0 = readl(ESDCTL_BASE);
137 int ver = read_system_rev();
139 find_correct_chip = ver;
141 if (ver != CHIP_VERSION_NONE) {
142 /* Valid product revision found. Check actual silicon rev and
143 * NOT use the version from the ROM code. */
144 if (((ver >> 4) & 0xF) == 0x0) {
145 HAL_PLATFORM_EXTRA[39] = '1';
146 HAL_PLATFORM_EXTRA[41] = '0';
147 system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
148 system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
149 } else if (((ver >> 4) & 0xF) == 0x1) {
150 HAL_PLATFORM_EXTRA[39] = '1';
151 HAL_PLATFORM_EXTRA[41] = '1';
152 system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
153 system_rev |= 1 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
154 } else if (((ver >> 4) & 0xF) == 0x2) {
155 HAL_PLATFORM_EXTRA[39] = '2';
156 HAL_PLATFORM_EXTRA[41] = '0';
157 system_rev |= 2 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
158 system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
160 HAL_PLATFORM_EXTRA[39] = 'x';
161 HAL_PLATFORM_EXTRA[41] = 'x';
162 system_rev |= 1 << MAJOR_NUMBER_OFFSET ;/*Major Number*/
163 system_rev |= 0 << MINOR_NUMBER_OFFSET ;/*Minor Number*/
164 find_correct_chip = CHIP_VERSION_UNKNOWN;
168 if ((esdmisc & 0x4) == 0) {
169 HAL_PLATFORM_EXTRA[48] = 'S';
171 if ((esdctl0 & 0x30000) != 0x20000) {
172 HAL_PLATFORM_EXTRA[45] = '1';
173 HAL_PLATFORM_EXTRA[46] = '6';
176 // Mask all interrupts
177 writel(0xFFFFFFFF, AVIC_NIMASK);
179 // Make all interrupts do IRQ and not FIQ
180 // FIXME: Change this if you use FIQs.
181 writel(0, AVIC_INTTYPEH);
182 writel(0, AVIC_INTTYPEL);
188 // enable EPIT and start it with 32KHz input clock
189 writel(0x00010000, EPIT_BASE_ADDR + EPITCR);
191 // make sure reset is complete
192 while ((readl(EPIT_BASE_ADDR + EPITCR) & 0x10000) != 0) {
195 writel(0x030E0002, EPIT_BASE_ADDR + EPITCR);
196 writel(0x030E0003, EPIT_BASE_ADDR + EPITCR);
198 writel(0, EPIT_BASE_ADDR + EPITCMPR); // always compare with 0
200 if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
201 // increase the WDOG timeout value to the max
202 writew(readw(WDOG_BASE_ADDR) | 0xFF00, WDOG_BASE_ADDR);
205 // Perform any platform specific initializations
208 // Set up eCos/ROM interfaces
211 nfc_setup = (nfc_setup_func_t*)mxc_nfc_soc_setup;
214 // -------------------------------------------------------------------------
215 void hal_clock_initialize(cyg_uint32 period)
219 // This routine is called during a clock interrupt.
221 // Define this if you want to ensure that the clock is perfect (i.e. does
222 // not drift). One reason to leave it turned off is that it costs some
223 // us per system clock interrupt for this maintenance.
224 #undef COMPENSATE_FOR_CLOCK_DRIFT
226 void hal_clock_reset(cyg_uint32 vector, cyg_uint32 period)
230 // Read the current value of the clock, returning the number of hardware
231 // "ticks" that have occurred (i.e. how far away the current value is from
234 // Note: The "contract" for this function is that the value is the number
235 // of hardware clocks that have happened since the last interrupt (i.e.
236 // when it was reset). This value is used to measure interrupt latencies.
237 // However, since the hardware counter runs freely, this routine computes
238 // the difference between the current clock period and the number of hardware
239 // ticks left before the next timer interrupt.
240 void hal_clock_read(cyg_uint32 *pvalue)
244 // This is to cope with the test read used by tm_basic with
245 // CYGVAR_KERNEL_COUNTERS_CLOCK_LATENCY defined; we read the count ASAP
246 // in the ISR, *before* resetting the clock. Which returns 1tick +
247 // latency if we just use plain hal_clock_read().
248 void hal_clock_latency(cyg_uint32 *pvalue)
252 unsigned int hal_timer_count(void)
254 return (0xFFFFFFFF - readl(EPIT_BASE_ADDR + EPITCNR));
257 #define WDT_MAGIC_1 0x5555
258 #define WDT_MAGIC_2 0xAAAA
259 #define MXC_WDT_WSR 0x2
261 static unsigned int led_on = 0;
263 // Delay for some number of micro-seconds
265 void hal_delay_us(unsigned int usecs)
268 * This causes overflow.
269 * unsigned int delayCount = (usecs * 32768) / 1000000;
270 * So use the following one instead
272 unsigned int delayCount = (usecs * 512) / 15625;
274 if (delayCount == 0) {
278 // issue the service sequence instructions
279 if ((readw(WDOG_BASE_ADDR) & 4) != 0) {
280 writew(WDT_MAGIC_1, WDOG_BASE_ADDR + MXC_WDT_WSR);
281 writew(WDT_MAGIC_2, WDOG_BASE_ADDR + MXC_WDT_WSR);
284 writel(0x01, EPIT_BASE_ADDR + EPITSR); // clear the compare status bit
286 writel(delayCount, EPIT_BASE_ADDR + EPITLR);
288 while ((0x1 & readl(EPIT_BASE_ADDR + EPITSR)) == 0); // return until compare bit is set
289 if ((++led_on % 2000) == 0)
293 // -------------------------------------------------------------------------
295 // This routine is called to respond to a hardware interrupt (IRQ). It
296 // should interrogate the hardware and return the IRQ vector number.
297 int hal_IRQ_handler(void)
299 #ifdef HAL_EXTENDED_IRQ_HANDLER
302 // Use platform specific IRQ handler, if defined
303 // Note: this macro should do a 'return' with the appropriate
304 // interrupt number if such an extended interrupt exists. The
305 // assumption is that the line after the macro starts 'normal' processing.
306 HAL_EXTENDED_IRQ_HANDLER(index);
309 return CYGNUM_HAL_INTERRUPT_NONE; // This shouldn't happen!
316 void hal_interrupt_mask(int vector)
318 // diag_printf("6hal_interrupt_mask(vector=%d) \n", vector);
319 #ifdef HAL_EXTENDED_INTERRUPT_MASK
320 // Use platform specific handling, if defined
321 // Note: this macro should do a 'return' for "extended" values of 'vector'
322 // Normal vectors are handled by code subsequent to the macro call.
323 HAL_EXTENDED_INTERRUPT_MASK(vector);
327 void hal_interrupt_unmask(int vector)
329 // diag_printf("7hal_interrupt_unmask(vector=%d) \n", vector);
331 #ifdef HAL_EXTENDED_INTERRUPT_UNMASK
332 // Use platform specific handling, if defined
333 // Note: this macro should do a 'return' for "extended" values of 'vector'
334 // Normal vectors are handled by code subsequent to the macro call.
335 HAL_EXTENDED_INTERRUPT_UNMASK(vector);
339 void hal_interrupt_acknowledge(int vector)
342 // diag_printf("8hal_interrupt_acknowledge(vector=%d) \n", vector);
343 #ifdef HAL_EXTENDED_INTERRUPT_UNMASK
344 // Use platform specific handling, if defined
345 // Note: this macro should do a 'return' for "extended" values of 'vector'
346 // Normal vectors are handled by code subsequent to the macro call.
347 HAL_EXTENDED_INTERRUPT_ACKNOWLEDGE(vector);
351 void hal_interrupt_configure(int vector, int level, int up)
354 #ifdef HAL_EXTENDED_INTERRUPT_CONFIGURE
355 // Use platform specific handling, if defined
356 // Note: this macro should do a 'return' for "extended" values of 'vector'
357 // Normal vectors are handled by code subsequent to the macro call.
358 HAL_EXTENDED_INTERRUPT_CONFIGURE(vector, level, up);
362 void hal_interrupt_set_level(int vector, int level)
365 #ifdef HAL_EXTENDED_INTERRUPT_SET_LEVEL
366 // Use platform specific handling, if defined
367 // Note: this macro should do a 'return' for "extended" values of 'vector'
368 // Normal vectors are handled by code subsequent to the macro call.
369 HAL_EXTENDED_INTERRUPT_SET_LEVEL(vector, level);
372 // Interrupt priorities are not configurable.
375 unsigned int mxc_nfc_soc_setup(unsigned int pg_sz, unsigned int io_sz, unsigned int is_mlc)
377 unsigned int tmp, res = -1;
380 tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) | (1 << 9);
382 tmp = readw(NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF) & (~(1 << 9));
384 writew(tmp, NAND_REG_BASE + NAND_FLASH_CONFIG1_REG_OFF);
387 tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) | (1 << 30);
389 tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & (~(1 << 30));
391 writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
394 tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) | (1 << 31);
396 tmp = readl(CCM_BASE_ADDR + CLKCTL_RCSR) & (~(1 << 31));
398 writel(tmp, CCM_BASE_ADDR + CLKCTL_RCSR);
400 tmp = system_rev >> PART_NUMBER_OFFSET;
409 diag_printf("Unknown chip version: 0x%x\n", tmp);
415 static void check_correct_chip(void)
417 if (find_correct_chip == CHIP_VERSION_UNKNOWN) {
418 diag_printf("Unrecognized chip version: 0x%x!!!\n", read_system_rev());
419 diag_printf("Assuming chip version=0x%x\n", system_rev);
420 } else if (find_correct_chip == CHIP_VERSION_NONE) {
421 diag_printf("Unrecognized chip: 0x%x!!!\n", readl(IIM_BASE_ADDR + IIM_PREV_OFF));
425 RedBoot_init(check_correct_chip, RedBoot_INIT_LAST);