1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/karo_tx51.h> // Platform specific hardware definitions
51 #include CYGHWR_MEMORY_LAYOUT_H
53 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
54 #define PLATFORM_SETUP1 _platform_setup1
55 #define CYGHWR_HAL_ARM_HAS_MMU
57 #ifdef CYG_HAL_STARTUP_ROMRAM
58 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define TX51_NAND_PAGE_SIZE 2048
62 #define TX51_NAND_BLKS_PER_PAGE 64
64 #define DEBUG_LED_BIT 10
65 #define LED_GPIO_BASE GPIO4_BASE_ADDR
66 #define LED_MUX_OFFSET 0x1d0
67 #define LED_MUX_MODE 0x13
69 #define LED_ON LED_CTRL #1
70 #define LED_OFF LED_CTRL #0
72 #ifndef CYGOPT_HAL_ARM_TX51_DEBUG
80 #define CYGHWR_LED_MACRO LED_BLINK #\x
96 // switch user LED (GPIO4_10) on STK5
97 ldr r10, =LED_GPIO_BASE
101 movne r9, #(1 << DEBUG_LED_BIT) @ LED ON
102 moveq r9, #0 @ LED OFF
103 str r9, [r10, #GPIO_DR]
122 // initialize GPIO4_10 (PAD CSI2_D13) for LED on STK5
123 ldr r10, =LED_GPIO_BASE
125 ldr r9, [r10, #GPIO_GDIR]
126 orr r9, r9, #(1 << DEBUG_LED_BIT)
127 str r9, [r10, #GPIO_GDIR]
129 ldr r10, =IOMUXC_BASE_ADDR
130 mov r9, #LED_MUX_MODE
131 str r9, [r10, #LED_MUX_OFFSET]
133 mov r9, #(1 << DEBUG_LED_BIT) @ LED ON
134 str r9, [r10, #GPIO_DR]
137 #define DCDGEN(type, addr, data) .long type, addr, data
139 #define PLATFORM_PREAMBLE flash_header
141 // This macro represents the initial startup code for the platform
142 .macro _platform_setup1
143 KARO_TX51_SETUP_START:
150 ldr r1, =ROM_BASE_ADDR
151 ldr r11, [r1, #ROM_SI_REV_OFFSET]
155 ldr r0, =GPC_BASE_ADDR
156 cmp r11, #0x10 // r11 contains the silicon rev
157 ldrls r1, =0x1FC00000
158 ldrhi r1, =0x1A800000
161 // Explicitly disable L2 cache
162 mrc 15, 0, r0, c1, c0, 1
164 mcr 15, 0, r0, c1, c0, 1
166 // reconfigure L2 cache aux control reg
167 mov r0, #0xC0 // tag RAM
168 add r0, r0, #0x4 // data RAM
169 orr r0, r0, #(1 << 24) // disable write allocate delay
170 orr r0, r0, #(1 << 23) // disable write allocate combine
171 orr r0, r0, #(1 << 22) // disable write allocate
173 @ cc is still set from "cmp r11, #0x10" above
174 orrls r0, r0, #(1 << 25) @ disable write combine for TO 2 and lower revs
176 mcr 15, 1, r0, c9, c0, 2
184 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
186 #endif /* CYG_HAL_STARTUP_ROMRAM */
190 Normal_Boot_Continue:
193 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
196 @ Set up a stack [for calling C code]
197 ldr r1, =__startup_stack
198 ldr r2, =RAM_BANK0_BASE
205 /* Workaround for arm erratum #709718 */
206 @ Setup PRRR so device is always mapped to non-shared
207 mrc MMU_CP, 0, r1, c10, c2, 0 // Read Primary Region Remap Register
209 mcr MMU_CP, 0, r1, c10, c2, 0 // Write Primary Region Remap Register
213 mrc MMU_CP, 0, r1, MMU_Control, c0
214 orr r1, r1, #7 @ enable MMU bit
215 orr r1, r1, #0x800 @ enable z bit
216 orr r1, r1, #(1 << 28) @ Enable TEX remap, workaround for L1 cache issue
217 mcr MMU_CP, 0, r1, MMU_Control, c0
219 /* Workaround for arm errata #621766 */
220 mrc MMU_CP, 0, r1, MMU_Control, c0, 1
221 orr r1, r1, #(1 << 5) @ enable L1NEON bit
222 mcr MMU_CP, 0, r1, MMU_Control, c0, 1
224 mov pc, r2 @ Change address spaces
228 .endm @ _platform_setup1
230 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
233 * Set all MPROTx to be non-bufferable, trusted for R/W,
234 * not forced to user-mode.
236 ldr r0, =AIPS1_CTRL_BASE_ADDR
240 ldr r0, =AIPS2_CTRL_BASE_ADDR
243 .endm /* init_aips */
246 ldr r0, =WDOG_BASE_ADDR
254 ldr r0, =CCM_BASE_ADDR
255 ldr r1, [r0, #CLKCTL_CCR]
259 orr r1, r1, #(1 << 12)
260 str r1, [r0, #CLKCTL_CCR]
262 ldr r1, [r0, #CLKCTL_CCSR]
263 bic r1, #(1 << 9) /* switch lp_apm to OSC */
264 str r1, [r0, #CLKCTL_CCSR]
266 /* Gate off clocks to the peripherals first */
268 str r1, [r0, #CLKCTL_CCGR0]
270 str r1, [r0, #CLKCTL_CCGR1]
271 str r1, [r0, #CLKCTL_CCGR2]
272 str r1, [r0, #CLKCTL_CCGR3]
275 str r1, [r0, #CLKCTL_CCGR4]
277 str r1, [r0, #CLKCTL_CCGR5]
279 str r1, [r0, #CLKCTL_CCGR6]
281 /* Disable IPU and HSC dividers */
283 str r1, [r0, #CLKCTL_CCDR]
285 /* Make sure to switch the DDR away from PLL 1 */
286 ldr r1, CCM_CBCDR_VAL1
287 str r1, [r0, #CLKCTL_CBCDR]
288 /* make sure divider effective */
290 ldr r1, [r0, #CLKCTL_CDHIPR]
294 /* Switch ARM to step clock */
295 ldr r1, [r0, #CLKCTL_CCSR]
297 str r1, [r0, #CLKCTL_CCSR]
302 /* Switch peripheral to PLL 3 */
303 ldr r1, CCM_CBCMR_VAL1
304 str r1, [r0, #CLKCTL_CBCMR]
306 ldr r1, CCM_CBCDR_VAL2
307 str r1, [r0, #CLKCTL_CBCDR]
311 /* Switch peripheral to PLL 2 */
312 ldr r1, CCM_CBCDR_VAL1
313 str r1, [r0, #CLKCTL_CBCDR]
314 /* Use lp_apm (24MHz) source for perclk */
315 ldr r1, CCM_CBCMR_VAL2
316 str r1, [r0, #CLKCTL_CBCMR]
320 /* Set the platform clock dividers */
321 ldr r2, =PLATFORM_BASE_ADDR
322 ldr r1, PLATFORM_CLOCK_DIV
323 str r1, [r2, #PLATFORM_ICGC]
325 /* Run TO 3.0 at Full speed, for other TO's wait till we increase VDDGP */
329 str r1, [r0, #CLKCTL_CACRR]
331 /* Switch ARM back to PLL 1. */
333 str r1, [r0, #CLKCTL_CCSR]
336 @ ddr clock from PLL 1, all perclk dividers are 1 since using 24MHz
337 ldr r1, CCM_CBCDR_VAL3
338 str r1, [r0, #CLKCTL_CBCDR]
340 /* Restore the default values in the Gate registers */
342 str r1, [r0, #CLKCTL_CCGR0]
343 str r1, [r0, #CLKCTL_CCGR1]
344 str r1, [r0, #CLKCTL_CCGR2]
345 str r1, [r0, #CLKCTL_CCGR3]
346 str r1, [r0, #CLKCTL_CCGR4]
347 str r1, [r0, #CLKCTL_CCGR5]
348 str r1, [r0, #CLKCTL_CCGR6]
350 /* Use PLL 2 for UART's, get 66.5MHz from it */
351 ldr r1, CCM_CSCMR1_VAL
352 str r1, [r0, #CLKCTL_CSCMR1]
353 ldr r1, CCM_CSCDR1_VAL
354 str r1, [r0, #CLKCTL_CSCDR1]
356 /* make sure divider effective */
358 ldr r1, [r0, #CLKCTL_CDHIPR]
363 str r1, [r0, #CLKCTL_CCDR]
365 @ for cko - for ARM div by 8
367 orr r1, r1, #0x00000F0
368 str r1, [r0, #CLKCTL_CCOSR]
370 ldr r1, [r0, #CLKCTL_CCR]
371 bic r1, #(1 << 8) /* switch off FPM */
372 str r1, [r0, #CLKCTL_CCR]
376 .macro setup_pll pll_nr, mhz
377 ldr r2, BASE_ADDR_\pll_nr
378 ldr r1, PLL_VAL_0x1232
379 str r1, [r2, #PLL_DP_CTL] @ Set DPLL ON (set UPEN bit); BRMO=1
381 str r1, [r2, #PLL_DP_CONFIG] @ Enable auto-restart AREN bit
384 str r1, [r2, #PLL_DP_OP]
385 str r1, [r2, #PLL_DP_HFS_OP]
387 ldr r1, W_DP_MFD_\mhz
388 str r1, [r2, #PLL_DP_MFD]
389 str r1, [r2, #PLL_DP_HFS_MFD]
391 ldr r1, W_DP_MFN_\mhz
392 str r1, [r2, #PLL_DP_MFN]
393 str r1, [r2, #PLL_DP_HFS_MFN]
396 str r1, [r2, #PLL_DP_CONFIG] @ Assert LDREQ
399 ldr r1, PLL_VAL_0x1232
400 str r1, [r2, #PLL_DP_CTL]
402 ldr r1, [r2, #PLL_DP_CTL]
409 ldr r1, =M4IF_BASE_ADDR
410 ldr r0, M4IF_M4IF4_VAL
411 str r0, [r1, #M4IF_MIF4]
413 /* Configure M4IF registers, VPU and IPU given higher priority (=0x4) */
414 ldr r0, M4IF_FBPM0_VAL
415 str r0, [r1, #M4IF_FBPM0]
417 ldr r0, M4IF_FPWC_VAL
418 str r0, [r1, #M4IF_FPWC]
419 .endm /* init_m4if */
423 cmp r11, #0x10 // r11 contains the silicon rev
425 /* Decrease the DRAM SDCLK pads to HIGH Drive strength */
426 ldr r0, =IOMUXC_BASE_ADDR
429 /* Change the delay line configuration */
430 ldr r0, =ESDCTL_BASE_ADDR
432 str r1, [r0, #ESDCTL_ESDCDLY1]
434 str r1, [r0, #ESDCTL_ESDCDLY2]
436 str r1, [r0, #ESDCTL_ESDCDLY3]
438 str r1, [r0, #ESDCTL_ESDCDLY4]
440 str r1, [r0, #ESDCTL_ESDCDLY5]
444 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
445 #define PLATFORM_SETUP1
448 #define PLATFORM_VECTORS _platform_vectors
449 .macro _platform_vectors
453 .globl _KARO_STRUCT_SIZE
455 .word 0 // reserve space structure length
457 .globl _KARO_CECFG_START
460 .word 0 // reserve space for CE configuration
463 .globl _KARO_CECFG_END
468 .ascii "KARO TX51 " __DATE__ " " __TIME__
471 /* SDRAM timing setup */
475 #if SDRAM_SIZE <= SZ_128M
476 #define RA_BITS (13 - 11) /* row addr bits - 11 */
478 #define RA_BITS (14 - 11) /* row addr bits - 11 */
481 #define CA_BITS (10 - 8) /* 0-2: col addr bits - 8 3: rsrvd */
482 #define DSIZ 2 /* 0: D[31..16] 1: D[15..D0] 2: D[31..0] 3: rsrvd */
483 #define SREFR 3 /* 0: disabled 1-5: 2^n rows/clock *: rsrvd */
484 #define SRT 0 /* 0: disabled *: 1: self refr. ... */
485 #define PWDT 0 /* 0: disabled 1: precharge pwdn
486 2: pwdn after 64 clocks 3: pwdn after 128 clocks */
487 #define ESDCTL_VAL (0x80000000 | (SREFR << 28) | (RA_BITS << 24) | (CA_BITS << 20) | \
488 (DSIZ << 16) | (SRT << 14) | (PWDT << 12))
490 #define SDRAM_CLK 200
491 #define NS_TO_CK(ns) (((ns) * SDRAM_CLK + 999) / 1000)
493 .macro CK_VAL, name, clks, offs
497 .set \name, \clks - \offs
501 .macro NS_VAL, name, ns, offs
505 CK_VAL \name, NS_TO_CK(\ns), \offs
509 #if SDRAM_SIZE <= SZ_128M
511 NS_VAL tRFC, 125, 10 /* clks - 10 (0..15) */
512 NS_VAL tXSR, 138, 25 /* clks - 25 (0..15) */
513 NS_VAL tXP, 25, 1 /* clks - 1 (0..7) */
514 CK_VAL tWTR, 1, 1 /* clks - 1 (0..1) */
515 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
516 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
517 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
518 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
519 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
520 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
521 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
523 /* MT46H64M32LF-5 or -6 */
524 NS_VAL tRFC, 72, 10 /* clks - 10 (0..15) */
525 NS_VAL tXSR, 113, 25 /* clks - 25 (0..15) */
526 CK_VAL tXP, 2, 1 /* clks - 1 (0..7) */
527 CK_VAL tWTR, 2, 1 /* clks - 1 (0..1) */
528 NS_VAL tRP, 18, 2 /* clks - 2 (0..3) */
529 CK_VAL tMRD, 2, 1 /* clks - 1 (0..3) */
530 NS_VAL tWR, 15, 2 /* clks - 2 (0..1) */
531 NS_VAL tRAS, 42, 1 /* clks - 1 (0..15) */
532 NS_VAL tRRD, 12, 1 /* clks - 1 (0..3) */
533 NS_VAL tRCD, 18, 1 /* clks - 1 (0..7) */
534 NS_VAL tRC, 60, 1 /* 0: 20 *: clks - 1 (0..15) */
537 #define ESDCFG_VAL ((tRFC << 28) | (tXSR << 24) | (tXP << 21) | \
538 (tWTR << 20) | (tRP << 18) | (tMRD << 16) | \
539 (tRAS << 12) | (tRRD << 10) | (tWR << 7) | \
540 (tRCD << 4) | (tRC << 0))
544 #define ESDMISC_RALAT(n) (((n) & 0x3) << 7)
545 #define ESDMISC_DDR2_EN(n) (((n) & 0x1) << 4)
546 #define ESDMISC_DDR_EN(n) (((n) & 0x1) << 3)
547 #define ESDMISC_AP(n) (((n) & 0xf) << 16)
548 #define ESDMISC_VAL (ESDMISC_AP(10) | ESDMISC_RALAT(RALAT) | \
549 (LHD << 5) | ESDMISC_DDR2_EN(0) | ESDMISC_DDR_EN(0))
559 .long 0 // 0x97f40000 - 0x1000
563 .long 0 // hab_super_root_key
567 #ifndef RAM_BANK1_SIZE
568 .long RAM_BANK0_BASE + SDRAM_SIZE - REDBOOT_OFFSET
570 .long RAM_BANK1_BASE + RAM_BANK1_SIZE - REDBOOT_OFFSET
573 .long 0xB17219E9 // Fixed. can't change.
575 .long dcd_end - dcd_start
577 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, 0x80000000)
578 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x04008008)
579 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
580 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00008010)
581 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00338018)
582 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL0, ESDCTL_VAL)
583 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG0, ESDCFG_VAL)
584 #ifdef RAM_BANK1_SIZE
585 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCTL1, ESDCTL_VAL)
586 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDCFG1, ESDCFG_VAL)
588 DCDGEN(4, ESDCTL_BASE_ADDR + 0x34, 0x00020000 | ((RALAT & 0x3) << 29))
589 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDMISC, ESDMISC_VAL)
590 DCDGEN(4, ESDCTL_BASE_ADDR + ESDCTL_ESDSCR, 0x00000000)
593 .long REDBOOT_IMAGE_SIZE
596 SRC_BASE_ADDR_W: .long SRC_BASE_ADDR
597 WDOG_BASE_ADDR_W: .long WDOG_BASE_ADDR
598 AIPS1_PARAM: .word 0x77777777
599 M4IF_FBPM0_VAL: .word 0x00000103
600 M4IF_M4IF4_VAL: .word 0x00230185
601 M4IF_FPWC_VAL: .word 0x00240126
602 MXC_REDBOOT_ROM_START: .long SDRAM_BASE_ADDR + SDRAM_SIZE - REDBOOT_OFFSET
603 CCM_CBCDR_VAL1: .word 0x19239145
604 CCM_CBCDR_VAL2: .word 0x13239145
606 CCM_CBCDR_VAL3: .word 0x59E35100
608 CCM_CBCDR_VAL3: .word 0x21E35100
610 CCM_CBCMR_VAL1: .word 0x000010C0
611 CCM_CBCMR_VAL2: .word 0x000020C0
612 CCM_CSCMR1_VAL: .word 0xA5A2A020
613 CCM_CSCDR1_VAL: .word 0x00C30321
614 BASE_ADDR_PLL1: .long PLL1_BASE_ADDR
615 BASE_ADDR_PLL2: .long PLL2_BASE_ADDR
616 BASE_ADDR_PLL3: .long PLL3_BASE_ADDR
617 PLL_VAL_0x1232: .word 0x1232
618 W_DP_OP_800: .word DP_OP_800
619 W_DP_MFD_800: .word DP_MFD_800
620 W_DP_MFN_800: .word DP_MFN_800
621 W_DP_OP_700: .word DP_OP_700
622 W_DP_MFD_700: .word DP_MFD_700
623 W_DP_MFN_700: .word DP_MFN_700
624 W_DP_OP_400: .word DP_OP_400
625 W_DP_MFD_400: .word DP_MFD_400
626 W_DP_MFN_400: .word DP_MFN_400
627 W_DP_OP_532: .word DP_OP_532
628 W_DP_MFD_532: .word DP_MFD_532
629 W_DP_MFN_532: .word DP_MFN_532
630 W_DP_OP_665: .word DP_OP_665
631 W_DP_MFD_665: .word DP_MFD_665
632 W_DP_MFN_665: .word DP_MFN_665
633 W_DP_OP_216: .word DP_OP_216
634 W_DP_MFD_216: .word DP_MFD_216
635 W_DP_MFN_216: .word DP_MFN_216
636 PLATFORM_CLOCK_DIV: .word 0x00000124
638 /*----------------------------------------------------------------------*/
639 /* end of hal_platform_setup.h */
640 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */