1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
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34 // this file might be covered by the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
44 #include CYGBLD_HAL_PLATFORM_H
46 #include <cyg/infra/cyg_type.h> // base types
47 #include <cyg/infra/cyg_trac.h> // tracing macros
48 #include <cyg/infra/cyg_ass.h> // assertion macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_arch.h> // Register state info
52 #include <cyg/hal/hal_diag.h>
53 #include <cyg/hal/hal_intr.h> // Interrupt names
54 #include <cyg/hal/hal_cache.h>
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/fsl_board.h> // Platform specifics
58 #include <cyg/infra/diag.h> // diag_printf
60 // All the MM table layout is here:
61 #include <cyg/hal/hal_mm.h>
63 externC void* memset(void *, int, size_t);
65 void hal_mmu_init(void)
67 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
71 * Set the TTB register
73 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
76 * Set the Domain Access Control Register
78 i = ARM_ACCESS_DACR_DEFAULT;
79 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
82 * First clear all TT entries - ie Set them to Faulting
84 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
86 /* Actual Virtual Size Attributes Function */
87 /* Base Base MB cached? buffered? access permissions */
88 /* xxx00000 xxx00000 */
89 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
90 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
91 X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
93 X_ARM_MMU_SECTION(0x800, 0x000, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0x800, 0x800, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
95 #ifndef CYGHWR_HAL_ARM_MEM1
96 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
98 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
100 X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
101 X_ARM_MMU_SECTION(0xB50, 0xB50, 0x8, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* PSRAM */
102 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
106 // Platform specific initialization
109 void plf_hardware_init(void)
111 volatile unsigned int *pMuxCtl, *pMuxComCtl;
112 volatile unsigned short *pPBCCtl;
115 // Setup IOMUX for UARTs
116 pMuxCtl = (volatile unsigned int *)(IOMUX_AP_BASE_ADDR);
117 pMuxComCtl = (volatile unsigned int *)(IOMUX_COM_BASE_ADDR);
120 // U1_TXD -> U1_TXD (MUX0_OUT, MUX0_IN)
121 pMuxCtl[0x28>>2] = (pMuxCtl[0x28>>2] & (0xFF00FFFF)) | (0x12 << 16);
122 // U1_RXD -> U1_RXD (MUX0_OUT, MUX0_IN)
123 pMuxCtl[0x2C>>2] = (pMuxCtl[0x2C>>2] & (0x00FFFFFF)) | (0x12 << 24);
126 // U2_RXD -> U2_RXD (MUX0_OUT, MUX0_IN)
127 pMuxCtl[0x34>>2] = (pMuxCtl[0x34>>2] & (0x00FFFFFF)) | (0x12 << 24);
128 // U2_TXD -> U2_TXD (MUX0_OUT, MUX0_IN)
129 pMuxCtl[0x34>>2] = (pMuxCtl[0x34>>2] & (0xFF00FFFF)) | (0x12 << 16);
132 // USB_DAT_VP -> U3CE_TXD (MUX4_OUT, NONE_IN)
133 pMuxComCtl[0] = (pMuxComCtl[0] & (0xFFFFFF00)) | 0x40;
134 // USB_SE0_VM -> U3CE_RXD (MUX2_OUT, NONE_IN)
135 pMuxComCtl[0] = (pMuxComCtl[0] & (0xFFFF00FF)) | (0x20 << 8);
138 pPBCCtl = (volatile unsigned short *)(PBC_BASE + 0x4);
140 //Enable UART transceivers also reset the Ethernet/external UART
142 for (i = 0; i < 100000; i++) {
145 writew(0x3, PBC_BCTL1_CLR);
146 for (i = 0; i < 1000000; i++) {
149 readb(BOARD_CS_UART_BASE + 0x8);
150 readb(BOARD_CS_UART_BASE + 0x7);
151 readb(BOARD_CS_UART_BASE + 0x8);
152 readb(BOARD_CS_UART_BASE + 0x7);
155 #include CYGHWR_MEMORY_LAYOUT_H
157 typedef void code_fun(void);
159 void board_program_new_stack(void *func)
161 register CYG_ADDRESS stack_ptr asm("sp");
162 register CYG_ADDRESS old_stack asm("r4");
163 register code_fun *new_func asm("r0");
164 old_stack = stack_ptr;
165 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
166 new_func = (code_fun*)func;
168 stack_ptr = old_stack;