1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 //=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //===========================================================================
45 #include <pkgconf/system.h> // System-wide configuration info
46 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
47 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
48 #include <cyg/hal/hal_soc.h> // Variant specific hardware definitions
49 #include <cyg/hal/hal_mmu.h> // MMU definitions
50 #include <cyg/hal/fsl_board.h> // Platform specific hardware definitions
52 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
53 #define PLATFORM_SETUP1 _platform_setup1
54 #define CYGHWR_HAL_ARM_HAS_MMU
56 #ifdef CYG_HAL_STARTUP_ROMRAM
57 #define CYGSEM_HAL_ROM_RESET_USES_JUMP
61 #define CYGHWR_HAL_ROM_VADDR 0x0
64 #define UNALIGNED_ACCESS_ENABLE
65 #define SET_T_BIT_DISABLE
66 #define BRANCH_PREDICTION_ENABLE
69 //#define TURN_OFF_IMPRECISE_ABORT
71 // This macro represents the initial startup code for the platform
72 // r11 is reserved to contain chip rev info in this file
73 .macro _platform_setup1
74 FSL_BOARD_SETUP_START:
77 * - invalidate I/D cache/TLB and drain write buffer;
78 * - invalidate L2 cache
80 * - branch predictions
82 #ifdef TURN_OFF_IMPRECISE_ABORT
89 mcr 15, 0, r0, c7, c7, 0 /* invalidate I cache and D cache */
90 mcr 15, 0, r0, c8, c7, 0 /* invalidate TLBs */
91 mcr 15, 0, r0, c7, c10, 4 /* Drain the write buffer */
93 mov r0, #SDRAM_NON_FLASH_BOOT
94 ldr r1, AVIC_VECTOR0_ADDR_W
95 str r0, [r1] // for checking boot source from nand, nor or sdram
106 mov r11, #CHIP_REV_1_0
107 ldr r0, IIM_SREV_REG_VAL
110 movne r11, #CHIP_REV_2_0
111 init_cs0_async_start:
114 /* If SDRAM has been setup, bypass clock/WEIM setup */
115 cmp pc, #SDRAM_BASE_ADDR
117 cmp pc, #(SDRAM_BASE_ADDR + SDRAM_SIZE)
118 blo HWInitialise_skip_SDRAM_setup
120 mov r0, #NOR_FLASH_BOOT
121 ldr r1, AVIC_VECTOR0_ADDR_W
129 /* Assuming DDR memory first */
130 //init_drive_strength_ddr
132 /* Testing if it is truly DDR */
133 ldr r1, SDRAM_COMPARE_CONST1
134 mov r0, #SDRAM_BASE_ADDR
136 ldr r2, SDRAM_COMPARE_CONST2
140 beq HWInitialise_skip_SDRAM_setup
142 /* Reach here ONLY when SDR */
143 init_drive_strength_sdr
145 /* Test to make sure SDR */
146 ldr r1, SDRAM_COMPARE_CONST1
147 mov r0, #SDRAM_BASE_ADDR
149 ldr r2, SDRAM_COMPARE_CONST2
153 beq HWInitialise_skip_SDRAM_setup
155 /* Reach hear means memory setup problem. Try to
156 * increase the HCLK divider */
157 ldr r0, CRM_AP_BASE_ADDR_W
158 ldr r1, [r0, #CRM_AP_ACDR]
163 str r1, [r0, #CRM_AP_ACDR]
167 b loop_forever /* shouldn't get here */
169 HWInitialise_skip_SDRAM_setup:
172 add r2, r0, #0x800 // 2K window
174 blo Normal_Boot_Continue
176 bhi Normal_Boot_Continue
178 /* Copy image from flash to SDRAM first */
179 ldr r1, MXC_REDBOOT_ROM_START
181 1: ldmia r0!, {r3-r10}
187 and r0, pc, r1 /* offset of pc */
188 ldr r1, MXC_REDBOOT_ROM_START
196 mov r0, #NAND_FLASH_BOOT
197 ldr r1, AVIC_VECTOR0_ADDR_W
200 ldr r1, AVIC_VECTOR1_ADDR_W
203 mov r0, #NFC_BASE; //r0: nfc base. Reloaded after each page copying
204 mov r1, #0x800 //r1: starting flash addr to be copied. Updated constantly
205 add r2, r0, #0x200 //r2: end of 1st RAM buf. Doesn't change
206 add r12, r0, #0xE00 //r12: NFC register base. Doesn't change
207 ldr r14, MXC_REDBOOT_ROM_START
208 add r13, r14, #REDBOOT_IMAGE_SIZE //r13: end of SDRAM address for copying. Doesn't change
209 add r14, r14, r1 //r14: starting SDRAM address for copying. Updated constantly
211 //unlock internal buffer
216 // writew(FLASH_Read_Mode1, NAND_FLASH_CMD_REG);
218 strh r3, [r12, #NAND_FLASH_CMD_REG_OFF]
219 mov r3, #NAND_FLASH_CONFIG2_FCMD_EN;
220 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
223 // start_nfc_addr_ops(ADDRESS_INPUT_READ_PAGE, addr, nflash_dev_info->base_mask);
225 do_addr_input //1st addr cycle
227 do_addr_input //2nd addr cycle
229 do_addr_input //3rd addr cycle
231 // NFC_DATA_OUTPUT(buf, FDO_PAGE_SPARE_VAL);
232 // writew(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN,
233 // NAND_FLASH_CONFIG1_REG);
234 mov r3, #(NAND_FLASH_CONFIG1_INT_MSK | NAND_FLASH_CONFIG1_ECC_EN)
235 strh r3, [r12, #NAND_FLASH_CONFIG1_REG_OFF]
237 // writew(buf_no, RAM_BUFFER_ADDRESS_REG);
239 strh r3, [r12, #RAM_BUFFER_ADDRESS_REG_OFF]
240 // writew(FDO_PAGE_SPARE_VAL & 0xFF, NAND_FLASH_CONFIG2_REG);
241 mov r3, #FDO_PAGE_SPARE_VAL
242 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
246 // check for bad block
247 mov r3, r1, lsl #(32-5-9)
248 cmp r3, #(512 << (32-5-9))
250 add r4, r0, #0x800 //r3 -> spare area buf 0
255 // really sucks. Bad block!!!!
258 // even suckier since we already read the first page!
259 sub r14, r14, #512 //rewind 1 page for the sdram pointer
260 sub r1, r1, #512 //rewind 1 page for the flash pointer
262 add r1, r1, #(32*512)
266 1: ldmia r0!, {r3-r10}
271 bge NAND_Copy_Main_done
278 Normal_Boot_Continue:
283 #ifdef CYG_HAL_STARTUP_ROMRAM /* enable running from RAM */
284 /* Copy image from flash to SDRAM first */
287 ldr r1, MXC_REDBOOT_ROM_START
289 beq HWInitialise_skip_SDRAM_copy
291 add r2, r0, #REDBOOT_IMAGE_SIZE
293 1: ldmia r0!, {r3-r10}
299 and r0, pc, r1 /* offset of pc */
300 ldr r1, =(SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000 + 0x8)
306 #endif /* CYG_HAL_STARTUP_ROMRAM */
310 HWInitialise_skip_SDRAM_copy:
314 * IOMUX/PBC setup is done in C function plf_hardware_init() for simplicity
318 // Set up a stack [for calling C code]
319 ldr r1, =__startup_stack
320 ldr r2, =RAM_BANK0_BASE
328 mrc MMU_CP, 0, r1, MMU_Control, c0 // get c1 value to r1 first
329 orr r1, r1, #7 // enable MMU bit
330 mcr MMU_CP, 0, r1, MMU_Control, c0
331 mov pc,r2 /* Change address spaces */
337 // Save shadow copy of BCR, also hardware configuration
341 str r9, [r1] // Saved far above...
343 .endm // _platform_setup1
345 #else // defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
346 #define PLATFORM_SETUP1
349 /* Allow all 3 masters to have access to these shared peripherals */
351 ldr r0, SPBA_CTRL_BASE_ADDR_W
352 mov r1, #0x7 /* allow all 3 masters access */
369 .endm /* init_spba */
371 /* AIPS setup - Only setup MPROTx registers. The PACR default values are good.*/
374 * Set all MPROTx to be non-bufferable, trusted for R/W,
375 * not forced to user-mode.
377 ldr r0, AIPS1_CTRL_BASE_ADDR_W
378 ldr r1, AIPS1_PARAM_W
381 ldr r0, AIPS2_CTRL_BASE_ADDR_W
386 * Clear the on and off peripheral modules Supervisor Protect bit
387 * for SDMA to access them. Did not change the AIPS control registers
388 * (offset 0x20) access type
390 ldr r0, AIPS1_CTRL_BASE_ADDR_W
397 and r1, r1, #0x00FFFFFF
400 ldr r0, AIPS2_CTRL_BASE_ADDR_W
407 and r1, r1, #0x00FFFFFF
409 .endm /* init_aips */
411 /* MAX (Multi-Layer AHB Crossbar Switch) setup */
413 ldr r0, MAX_BASE_ADDR_W
414 /* MPR - priority is M3 > M0 > M1 > M2 */
416 str r1, [r0, #0x000] /* for S0 */
417 str r1, [r0, #0x100] /* for S1 */
418 str r1, [r0, #0x200] /* for S2 */
419 str r1, [r0, #0x300] /* for S3 */
420 str r1, [r0, #0x400] /* for S4 */
421 /* SGPCR - always park on last master */
423 str r1, [r0, #0x010] /* for S0 */
424 str r1, [r0, #0x110] /* for S1 */
425 str r1, [r0, #0x210] /* for S2 */
426 str r1, [r0, #0x310] /* for S3 */
427 str r1, [r0, #0x410] /* for S4 */
428 /* MGPCR - restore default values */
430 str r1, [r0, #0x800] /* for M0 */
431 str r1, [r0, #0x900] /* for M1 */
432 str r1, [r0, #0xA00] /* for M2 */
433 str r1, [r0, #0xB00] /* for M3 */
440 * After this step, AP domain is running out of PLL0 with:
442 Module Freq (MHz) Note
443 =========================================================================
445 AHB 133 known as "hclk" for ap_hclk and xxx_ahb_clk's
446 IP 66.5 ap_pclk and ap_com_pclk
449 * All other clocks can be figured out based on this.
452 * Step 1: Make CKOH controlled by CKOH.
455 ldr r0, IOMUX_COM_BASE_ADDR_W
459 ldr r0, CRM_AP_BASE_ADDR_W
460 str r1, [r0, #CRM_AP_ACSR]
462 * Step 2: Setup PLL0 - ADPLL for AP domain.
464 ldr r0, PLL0_BASE_ADDR_W
466 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
468 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON; BRMO=1 */
470 str r1, [r0, #PLL_DP_CTL]
473 * Set PLL0 to be 399MHz.
474 * MFI=5, PDF=0, MFD=25, MFN=3 ->
475 * PLL0=2*26MHzInput*(5+3/(25+1))/(0+1)=266 MHz
478 str r1, [r0, #PLL_DP_OP]
480 str r1, [r0, #PLL_DP_MFD]
482 str r1, [r0, #PLL_DP_MFN]
485 str r1, [r0, #PLL_DP_HFS_OP]
487 str r1, [r0, #PLL_DP_HFS_MFD]
489 str r1, [r0, #PLL_DP_HFS_MFN]
491 /* Now restart DPLL */
493 str r1, [r0, #PLL_DP_CTL]
495 ldr r1, [r0, #PLL_DP_CTL]
499 /* End of PLL0 setup with PLL0 being locked at 399MHz */
504 ldr r0, PLL2_BASE_ADDR_W
507 str r1, [r0, #PLL_DP_CTL] /* Set DPLL ON (set UPEN bit); BRMO=1 */
509 str r1, [r0, #PLL_DP_CONFIG] /* Enable auto-restart AREN bit */
512 * MFI=9, PDF=1, MFD=12, MFN=3 ->
513 * PLL2 = 2*26*(9+3/(12+1))/(1+1)=240 MHz
516 str r1, [r0, #PLL_DP_OP]
518 str r1, [r0, #PLL_DP_MFD]
520 str r1, [r0, #PLL_DP_MFN]
523 str r1, [r0, #PLL_DP_HFS_OP]
525 str r1, [r0, #PLL_DP_HFS_MFD]
527 str r1, [r0, #PLL_DP_HFS_MFN]
529 /* Now restart DPLL */
531 str r1, [r0, #PLL_DP_CTL]
534 ldr r1, [r0, #PLL_DP_CTL]
537 /* End of PLL2 setup with PLL2 being locked at 48MHz */
540 * Step 3: switching to DPLL for AP domain and restore default register values.
542 // AP CKO/CKOH selected
543 ldr r0, SRC_BASE_ADDR_W
544 ldr r1, [r0, #SRC_SSCR]
546 str r1, [r0, #SRC_SSCR]
547 ldr r0, CRM_AP_BASE_ADDR_W
548 /* Default CKOH as AP_CLK with div by 10 */
549 //orr r1, r1, #0x5600 /* HCLK */
550 ldr r1, [r0, #CRM_AP_ACR]
554 str r1, [r0, #CRM_AP_ACR]
558 str r1, [r0, #CRM_AP_ACDR] /* ARM core=266MHz, AHB=66.5MHz, IP=66.5MHz */
560 str r1, [r0, #CRM_AP_ASCSR] /* Select USB PLL for CS CLK */
562 str r1, [r0, #CRM_AP_ACSR] /* select DPLL for AP domain at new freq */
563 ldr r1, CRM_AP_ACDER_W
564 str r1, [r0, #CRM_AP_ACDER] /* set nfc_div=5 (5+1 actual divider) */
566 str r1, [r0, #CRM_AP_ACGCR] /* restore default */
568 str r1, [r0, #CRM_AP_ARCGR] /* restore default */
571 * Only when NOT directly booting from SDRAM:
572 * ARM core=266MHz, AHB=133MHz, IP=66.5MHz.
573 * This is to work around the booting problem with RVD on EVB only.
574 * Brassboard is fine.
576 ldr r0, CRM_AP_BASE_ADDR_W
578 str r1, [r0, #CRM_AP_ACDR]
580 // SD clock input select - usb_clk. divider changed to 1
582 add r1, r1, #0x00000002
583 str r1, [r0, #CRM_AP_APR]
584 .endm /* init_clock */
588 /* Configure M3IF registers */
591 * M3IF Control Register (M3IFCTL)
592 * MRRP[0] = TMAX not on priority list (0 << 0) = 0x00000000
593 * MRRP[1] = SMIF not on priority list (0 << 0) = 0x00000000
594 * MRRP[2] = MAX0 not on priority list (0 << 0) = 0x00000000
595 * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000
596 * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000
597 * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000
598 * MRRP[6] = IPU on priority list (1 << 6) = 0x00000040
599 * MRRP[7] = SMIF-L2CC not on priority list (0 << 0) = 0x00000000
604 str r0, [r1] /* M3IF control reg */
605 .endm /* init_m3if */
607 /* CS0 sync mode setup */
610 * Sync mode (AHB Clk = 133MHz ; BCLK = 44.3MHz):
612 /* Flash reset command */
613 ldr r0, =CS0_BASE_ADDR
631 /* Write flash config register */
634 /* Flash reset command */
638 ldr r0, =WEIM_BASE_ADDR
645 .endm /* init_cs0_sync */
647 /* CS0 async mode setup */
648 .macro init_cs0_async
649 /* Async flash mode */
650 ldr r0, =WEIM_CTRL_CS0
651 ldr r1, WEIM_CSCRU_0x0000CC03
653 ldr r1, WEIM_CSCRL_0xA0330D01
655 ldr r1, WEIM_CSCRA_0x00220800
657 .endm /* init_cs0_async */
659 /* CPLD on CS4 setup */
661 ldr r0, =WEIM_CTRL_CS4
669 ldr r0, CS4_BASE_ADDR_W
675 ldr r0, =WEIM_CTRL_CS4
688 .macro init_ddr_sdram
689 ldr r0, ESDCTL_BASE_W
691 * Configure Enhanced SDRAM Miscellaneous Register (ESDMISC) Register
692 * Set to DDR Mode (Not SDR), Do a delay line reset
693 * as the EMI AHB clock was changed
695 mov r1, #0xC // set ESDMISC reg
697 // Hold for more than 200ns
704 * Configure Enhanced SDRAM Configuration Register 0
705 * (ESDCFG0) Register. XP=2 MRD=2 RAS=6 CAS=3 Clocks
707 ldr r1, SDRAM_0x00395728
711 * Precharge all rows (ROW/COL Muxing NOT used outside
712 * NORMAL Mode); MODE=PRECHARGE ALL.
714 ldr r1, SDRAM_0x92210080
717 /* PRECHARGE ALL (A10=1). */
720 add r12, r12, #0x00000400
722 /* Run two refresh cycles; MODE=AUTO REFRESH */
723 ldr r1, SDRAM_0xA2210080
726 /* AUTO REFRESH 2 times */
733 * Configure DDRAM Operating mode to Load Mode
734 * Register Command; MODE=LOAD MODE REGISTER.
736 ldr r1, SDRAM_0xB2210080
742 add r12, r12, #0x00000033
745 /* Load Extended Mode register */
750 * Put controller in Normal mode. SDRAM now ready for
751 * accesses; Configure CSD0 ESDCTL0 and go into Normal
752 * Read/Write Mode; 16-bit[D0..D15]; BL=8; row=13;
753 * col=10; MODE=Normal
755 ldr r1, SDRAM_0x82216080
763 /* Dummy write into DDRAM */
764 ldr r1, SDRAM_0xC001C001
768 /* Dummy Read From DDRAM */
769 ldr r1, SDRAM_BASE_ADDR_W
777 /* r3 = value for ESDCTL0
778 * r4 = burst mode vs full-page mode */
779 .macro init_sdr_sdram
780 ldr r0, ESDCTL_BASE_W
781 mov r2, #SDRAM_BASE_ADDR
782 ldr r1, SDRAM_0x0075E73A
784 ldr r1, =0x2 // reset
789 // Hold for more than 200ns
795 ldr r1, SDRAM_0x92126080
799 add r12, r12, #0x00000400
801 ldr r1, SDRAM_0xA2126080
808 ldr r1, SDRAM_0xB2126180
820 .macro do_wait_op_done
822 ldrh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
823 ands r3, r3, #NAND_FLASH_CONFIG2_INT_DONE
826 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
827 .endm // do_wait_op_done
831 strh r3, [r12, #NAND_FLASH_ADD_REG_OFF]
832 mov r3, #NAND_FLASH_CONFIG2_FADD_EN
833 strh r3, [r12, #NAND_FLASH_CONFIG2_REG_OFF]
835 .endm // do_addr_input
837 /* Required for MXC91221 PASS 2 for 133MHz SDR */
838 .macro init_drive_strength_sdr
839 ldr r0, IOMUX_COM_BASE_ADDR_W
855 /* Required for DDR */
856 .macro init_drive_strength_ddr
857 ldr r0, IOMUX_COM_BASE_ADDR_W
877 #define PLATFORM_VECTORS _platform_vectors
878 .macro _platform_vectors
879 .globl _board_BCR, _board_CFG
880 _board_BCR: .long 0 // Board Control register shadow
881 _board_CFG: .long 0 // Board Configuration (read at RESET)
884 L2CACHE_PARAM: .word 0x00030024
885 IIM_SREV_REG_VAL: .word IIM_BASE_ADDR + IIM_SREV_OFF
886 AIPS1_CTRL_BASE_ADDR_W: .word AIPS1_CTRL_BASE_ADDR
887 AIPS2_CTRL_BASE_ADDR_W: .word AIPS2_CTRL_BASE_ADDR
888 CS4_BASE_ADDR_W: .word CS4_BASE_ADDR
889 AIPS1_PARAM_W: .word 0x77777777
890 MAX_BASE_ADDR_W: .word MAX_BASE_ADDR
891 MAX_PARAM1: .word 0x00000321
892 RVAL_WVAL_W: .word 0x515
893 CLKCTL_BASE_ADDR_W: .word CLKCTL_BASE_ADDR
894 PLL0_BASE_ADDR_W: .word PLL0_BASE_ADDR
895 CRM_AP_BASE_ADDR_W: .word CRM_AP_BASE_ADDR
896 SRC_BASE_ADDR_W: .word SRC_BASE_ADDR
897 IOMUX_COM_BASE_ADDR_W: .word IOMUX_COM_BASE_ADDR
898 PLL2_BASE_ADDR_W: .word PLL2_BASE_ADDR
899 SPBA_CTRL_BASE_ADDR_W: .word SPBA_CTRL_BASE_ADDR
900 WEIM_CSCRU_0x0000CC03: .word 0x0000CC03
901 WEIM_CSCRL_0xA0330D01: .word 0xA0330D01
902 WEIM_CSCRA_0x00220800: .word 0x00220800
903 ESDCTL_BASE_W: .word ESDCTL_BASE
904 SDRAM_BASE_ADDR_W: .word SDRAM_BASE_ADDR
905 M3IF_BASE_W: .word M3IF_BASE
906 CRM_AP_ACDER_W: .word 0x59155912
907 SDRAM_0x92126080: .word 0x92126080
908 SDRAM_0xA2126080: .word 0xA2126080
909 SDRAM_0xB2126180: .word 0xB2126180
910 SDRAM_0x0075E73A: .word 0x0075E73A
911 SDRAM_0x00395728: .word 0x00395728
912 SDRAM_0x92210080: .word 0x92210080
913 SDRAM_0xA2210080: .word 0xA2210080
914 SDRAM_0xB2210080: .word 0xB2210080
915 SDRAM_0x82216080: .word 0x82216080
916 SDRAM_0xC001C001: .word 0xC001C001
917 SDRAM_COMPARE_CONST1: .word 0x55555555
918 SDRAM_COMPARE_CONST2: .word 0xAAAAAAAA
919 MXC_REDBOOT_ROM_START: .word SDRAM_BASE_ADDR + SDRAM_SIZE - 0x100000
920 CONST_0x0FFF: .word 0x0FFF
921 AVIC_VECTOR0_ADDR_W: .word MXCBOOT_FLAG_REG
922 AVIC_VECTOR1_ADDR_W: .word MXCFIS_FLAG_REG
924 /*---------------------------------------------------------------------------*/
925 /* end of hal_platform_setup.h */
926 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */