packages/hal/arm/mxc91321/i30030ads/v2_0/src/board_diag.c

   1 /*=============================================================================
   2 //
   3 //      board_diag.c
   4 //
   5 //      HAL diagnostic output code
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //===========================================================================*/
  41
  42 #include <pkgconf/hal.h>
  43
  44 #include <cyg/infra/cyg_type.h>         // base types
  45 #include <cyg/infra/cyg_trac.h>         // tracing macros
  46 #include <cyg/infra/cyg_ass.h>          // assertion macros
  47
  48 #include <cyg/hal/hal_arch.h>           // basic machine info
  49 #include <cyg/hal/hal_intr.h>           // interrupt macros
  50 #include <cyg/hal/hal_io.h>             // IO macros
  51 #include <cyg/hal/hal_diag.h>
  52 #include <cyg/hal/hal_if.h>             // Calling-if API
  53 #include <cyg/hal/drv_api.h>            // driver API
  54 #include <cyg/hal/hal_misc.h>           // Helper functions
  55 #include <cyg/hal/hal_soc.h>            // Hardware definitions
  56 #include <cyg/hal/fsl_board.h>          // Platform specifics
  57
  58 static void cyg_hal_plf_duart_init(void);
  59 extern void cyg_hal_plf_serial_init(void);
  60
  61 #define CHECK_BOARD_VERSION(ret)
  62 #define CHECK_BOARD_VERSION_RET_VOID
  63
  64 #if 0
  65 #define CHECK_BOARD_VERSION(ret)     \
  66     do {                             \
  67         if (((*(volatile unsigned short*)0xB4000000) >> 8) < 0x15) \
  68                     return ret;      \
  69     } while (0);
  70
  71 #define CHECK_BOARD_VERSION_RET_VOID \
  72     do {                             \
  73         if (((*(volatile unsigned short*)0xB4000000) >> 8) < 0x15) \
  74                     return;          \
  75     } while (0);
  76 #endif
  77
  78 void cyg_hal_plf_comms_init(void)
  79 {
  80     static int initialized = 0;
  81
  82     if (initialized)
  83         return;
  84
  85     initialized = 1;
  86
  87     /* Setup GPIO and enable transceiver for UARTs */
  88     cyg_hal_plf_duart_init();
  89     cyg_hal_plf_serial_init();
  90 }
  91
  92 //=============================================================================
  93 // ST16552 DUART driver
  94 //=============================================================================
  95
  96 //-----------------------------------------------------------------------------
  97 // There are two serial ports.
  98 #define CYG_DEV_SERIAL_BASE_A    (BOARD_CS_UART_BASE + 0x0000) // port A
  99 #define CYG_DEV_SERIAL_BASE_B    (BOARD_CS_UART_BASE + 0x0010) // port B
 100
 101 //-----------------------------------------------------------------------------
 102 // Based on 14.7456 MHz xtal
 103 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==9600
 104 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 105 #define CYG_DEV_SERIAL_BAUD_LSB        0x60
 106 #endif
 107 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==19200
 108 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 109 #define CYG_DEV_SERIAL_BAUD_LSB        0x30
 110 #endif
 111 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==38400
 112 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 113 #define CYG_DEV_SERIAL_BAUD_LSB        0x18
 114 #endif
 115 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==57600
 116 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 117 #define CYG_DEV_SERIAL_BAUD_LSB        0x10
 118 #endif
 119 #if CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL_BAUD==115200
 120 #define CYG_DEV_SERIAL_BAUD_MSB        0x00
 121 #define CYG_DEV_SERIAL_BAUD_LSB        0x08
 122 #endif
 123
 124 #ifndef CYG_DEV_SERIAL_BAUD_MSB
 125 #error Missing/incorrect serial baud rate defined - CDL error?
 126 #endif
 127
 128 //-----------------------------------------------------------------------------
 129 // Define the serial registers. The board is equipped with a 16552
 130 // serial chip.
 131
 132 #ifdef EXT_UART_x16
 133 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT16
 134 #define HAL_READ_UINT_UART HAL_READ_UINT16
 135 typedef cyg_uint16 uart_width;
 136 #else  //_x8
 137 typedef cyg_uint8 uart_width;
 138 #define HAL_WRITE_UINT_UART HAL_WRITE_UINT8
 139 #define HAL_READ_UINT_UART HAL_READ_UINT8
 140 #endif
 141
 142 #define CYG_DEV_SERIAL_RHR   0x00 // receiver buffer register, read, dlab = 0
 143 #define CYG_DEV_SERIAL_THR   0x00 // transmitter holding register, write, dlab = 0
 144 #define CYG_DEV_SERIAL_DLL   0x00 // divisor latch (LS), read/write, dlab = 1
 145 #define CYG_DEV_SERIAL_IER   0x01 // interrupt enable register, read/write, dlab = 0
 146 #define CYG_DEV_SERIAL_DLM   0x01 // divisor latch (MS), read/write, dlab = 1
 147 #define CYG_DEV_SERIAL_IIR   0x02 // interrupt identification register, read, dlab = 0
 148 #define CYG_DEV_SERIAL_FCR   0x02 // fifo control register, write, dlab = 0
 149 #define CYG_DEV_SERIAL_AFR   0x02 // alternate function register, read/write, dlab = 1
 150 #define CYG_DEV_SERIAL_LCR   0x03 // line control register, read/write
 151 #define CYG_DEV_SERIAL_MCR   0x04
 152 #define CYG_DEV_SERIAL_MCR_A 0x04
 153 #define CYG_DEV_SERIAL_MCR_B 0x04
 154 #define CYG_DEV_SERIAL_LSR   0x05 // line status register, read
 155 #define CYG_DEV_SERIAL_MSR   0x06 // modem status register, read
 156 #define CYG_DEV_SERIAL_SCR   0x07 // scratch pad register
 157
 158 // The interrupt enable register bits.
 159 #define SIO_IER_ERDAI   0x01            // enable received data available irq
 160 #define SIO_IER_ETHREI  0x02            // enable THR empty interrupt
 161 #define SIO_IER_ELSI    0x04            // enable receiver line status irq
 162 #define SIO_IER_EMSI    0x08            // enable modem status interrupt
 163
 164 // The interrupt identification register bits.
 165 #define SIO_IIR_IP      0x01            // 0 if interrupt pending
 166 #define SIO_IIR_ID_MASK 0x0e            // mask for interrupt ID bits
 167 #define ISR_Tx          0x02
 168 #define ISR_Rx          0x04
 169
 170 // The line status register bits.
 171 #define SIO_LSR_DR      0x01            // data ready
 172 #define SIO_LSR_OE      0x02            // overrun error
 173 #define SIO_LSR_PE      0x04            // parity error
 174 #define SIO_LSR_FE      0x08            // framing error
 175 #define SIO_LSR_BI      0x10            // break interrupt
 176 #define SIO_LSR_THRE    0x20            // transmitter holding register empty
 177 #define SIO_LSR_TEMT    0x40            // transmitter register empty
 178 #define SIO_LSR_ERR     0x80            // any error condition
 179
 180 // The modem status register bits.
 181 #define SIO_MSR_DCTS    0x01            // delta clear to send
 182 #define SIO_MSR_DDSR    0x02            // delta data set ready
 183 #define SIO_MSR_TERI    0x04            // trailing edge ring indicator
 184 #define SIO_MSR_DDCD    0x08            // delta data carrier detect
 185 #define SIO_MSR_CTS     0x10            // clear to send
 186 #define SIO_MSR_DSR     0x20            // data set ready
 187 #define SIO_MSR_RI      0x40            // ring indicator
 188 #define SIO_MSR_DCD     0x80            // data carrier detect
 189
 190 // The line control register bits.
 191 #define SIO_LCR_WLS0   0x01             // word length select bit 0
 192 #define SIO_LCR_WLS1   0x02             // word length select bit 1
 193 #define SIO_LCR_STB    0x04             // number of stop bits
 194 #define SIO_LCR_PEN    0x08             // parity enable
 195 #define SIO_LCR_EPS    0x10             // even parity select
 196 #define SIO_LCR_SP     0x20             // stick parity
 197 #define SIO_LCR_SB     0x40             // set break
 198 #define SIO_LCR_DLAB   0x80             // divisor latch access bit
 199
 200 // The FIFO control register
 201 #define SIO_FCR_FCR0   0x01             // enable xmit and rcvr fifos
 202 #define SIO_FCR_FCR1   0x02             // clear RCVR FIFO
 203 #define SIO_FCR_FCR2   0x04             // clear XMIT FIFO
 204
 205 //-----------------------------------------------------------------------------
 206
 207 typedef struct {
 208     uart_width* base;
 209     cyg_int32 msec_timeout;
 210     int isr_vector;
 211 } channel_data_t;
 212
 213 static channel_data_t channels[] = {
 214 #ifdef CYGHWR_HAL_ARM_DUART_UARTA
 215 #if CYGHWR_HAL_ARM_DUART_UARTA != 0
 216     {(uart_width*)CYG_DEV_SERIAL_BASE_A, 1000, 0},
 217 #endif
 218 #endif
 219 #ifdef CYGHWR_HAL_ARM_DUART_UARTB
 220 #if CYGHWR_HAL_ARM_DUART_UARTB != 0
 221     {(uart_width*)CYG_DEV_SERIAL_BASE_B, 1000, 0}
 222 #endif
 223 #endif
 224 };
 225
 226 //-----------------------------------------------------------------------------
 227
 228 static void init_duart_channel(channel_data_t* __ch_data)
 229 {
 230     uart_width* base = __ch_data->base;
 231     uart_width lcr;
 232
 233     CHECK_BOARD_VERSION_RET_VOID;
 234
 235     // 8-1-no parity.
 236     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR,
 237                         SIO_LCR_WLS0 | SIO_LCR_WLS1);
 238
 239     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 240     lcr |= SIO_LCR_DLAB;
 241     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 242     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLL, CYG_DEV_SERIAL_BAUD_LSB);
 243     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_DLM, CYG_DEV_SERIAL_BAUD_MSB);
 244     lcr &= ~SIO_LCR_DLAB;
 245     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_LCR, lcr);
 246     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_FCR, 0x07);  // Enable & clear FIFO
 247 }
 248
 249 void cyg_hal_plf_duart_putc(void* __ch_data, cyg_uint8 c)
 250 {
 251     uart_width* base = ((channel_data_t*)__ch_data)->base;
 252     uart_width lsr;
 253
 254     CHECK_BOARD_VERSION_RET_VOID;
 255
 256     CYGARC_HAL_SAVE_GP();
 257
 258     do {
 259         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 260     } while ((lsr & SIO_LSR_THRE) == 0);
 261
 262     HAL_WRITE_UINT_UART(base+CYG_DEV_SERIAL_THR, c);
 263
 264     // Hang around until the character has been safely sent.
 265     do {
 266         HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 267     } while ((lsr & SIO_LSR_THRE) == 0);
 268
 269     CYGARC_HAL_RESTORE_GP();
 270 }
 271
 272 static cyg_bool cyg_hal_plf_duart_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 273 {
 274     uart_width* base = ((channel_data_t*)__ch_data)->base;
 275     uart_width lsr, ch16;
 276
 277     CHECK_BOARD_VERSION(false);
 278
 279     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_LSR, lsr);
 280     if ((lsr & SIO_LSR_DR) == 0)
 281         return false;
 282
 283     HAL_READ_UINT_UART(base+CYG_DEV_SERIAL_RHR, ch16);
 284
 285     *ch = (cyg_uint8) (ch16 & 0x00FF);
 286
 287     return true;
 288 }
 289
 290 cyg_uint8 cyg_hal_plf_duart_getc(void* __ch_data)
 291 {
 292     cyg_uint8 ch;
 293
 294     CYGARC_HAL_SAVE_GP();
 295
 296     while (!cyg_hal_plf_duart_getc_nonblock(__ch_data, &ch));
 297
 298     CYGARC_HAL_RESTORE_GP();
 299     return ch;
 300 }
 301
 302 static void cyg_hal_plf_duart_write(void* __ch_data, const cyg_uint8* __buf,
 303                                     cyg_uint32 __len)
 304 {
 305     CHECK_BOARD_VERSION_RET_VOID;
 306
 307     CYGARC_HAL_SAVE_GP();
 308
 309     while (__len-- > 0)
 310         cyg_hal_plf_duart_putc(__ch_data, *__buf++);
 311
 312     CYGARC_HAL_RESTORE_GP();
 313 }
 314
 315 static void cyg_hal_plf_duart_read(void* __ch_data, cyg_uint8* __buf,
 316                                    cyg_uint32 __len)
 317 {
 318     CHECK_BOARD_VERSION_RET_VOID;
 319
 320     CYGARC_HAL_SAVE_GP();
 321
 322     while (__len-- > 0)
 323         *__buf++ = cyg_hal_plf_duart_getc(__ch_data);
 324
 325     CYGARC_HAL_RESTORE_GP();
 326 }
 327
 328 cyg_bool cyg_hal_plf_duart_getc_timeout(void* __ch_data, cyg_uint8* ch)
 329 {
 330     int delay_count;
 331     channel_data_t* chan = (channel_data_t*)__ch_data;
 332     cyg_bool res;
 333
 334     CHECK_BOARD_VERSION(false);
 335
 336     CYGARC_HAL_SAVE_GP();
 337
 338     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 339     for (;;) {
 340         res = cyg_hal_plf_duart_getc_nonblock(__ch_data, ch);
 341         if (res || 0 == delay_count--)
 342             break;
 343
 344         CYGACC_CALL_IF_DELAY_US(100);
 345     }
 346
 347     CYGARC_HAL_RESTORE_GP();
 348     return res;
 349 }
 350
 351 static int cyg_hal_plf_duart_control(void *__ch_data,
 352                                      __comm_control_cmd_t __func, ...)
 353 {
 354     static int irq_state = 0;
 355     channel_data_t* chan = (channel_data_t*)__ch_data;
 356     uart_width ier;
 357     int ret = 0;
 358
 359     CHECK_BOARD_VERSION(-1);
 360
 361     CYGARC_HAL_SAVE_GP();
 362
 363     switch (__func) {
 364     case __COMMCTL_IRQ_ENABLE:
 365         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 366         HAL_INTERRUPT_SET_LEVEL(chan->isr_vector, 1);
 367         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 368         ier |= SIO_IER_ERDAI;
 369         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 370         irq_state = 1;
 371         break;
 372     case __COMMCTL_IRQ_DISABLE:
 373         ret = irq_state;
 374         irq_state = 0;
 375         HAL_INTERRUPT_MASK(chan->isr_vector);
 376         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 377         ier &= ~SIO_IER_ERDAI;
 378         HAL_WRITE_UINT_UART(chan->base+CYG_DEV_SERIAL_IER, ier);
 379         break;
 380     case __COMMCTL_DBG_ISR_VECTOR:
 381         ret = chan->isr_vector;
 382         break;
 383     case __COMMCTL_SET_TIMEOUT:
 384         {
 385             va_list ap;
 386
 387             va_start(ap, __func);
 388
 389             ret = chan->msec_timeout;
 390             chan->msec_timeout = va_arg(ap, cyg_uint32);
 391
 392             va_end(ap);
 393         }
 394         break;
 395     default:
 396         break;
 397     }
 398     CYGARC_HAL_RESTORE_GP();
 399     return ret;
 400 }
 401
 402 static int cyg_hal_plf_duart_isr(void *__ch_data, int* __ctrlc,
 403                                  CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 404 {
 405     channel_data_t* chan = (channel_data_t*)__ch_data;
 406     uart_width _iir;
 407     int res = 0;
 408     CYGARC_HAL_SAVE_GP();
 409
 410     HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_IIR, _iir);
 411     _iir &= SIO_IIR_ID_MASK;
 412
 413     *__ctrlc = 0;
 414     if ( ISR_Rx == _iir ) {
 415         uart_width c, lsr;
 416         cyg_uint8 c8;
 417         HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_LSR, lsr);
 418         if (lsr & SIO_LSR_DR) {
 419
 420             HAL_READ_UINT_UART(chan->base+CYG_DEV_SERIAL_RHR, c);
 421
 422             c8 = (cyg_uint8) (c & 0x00FF);
 423
 424             if (cyg_hal_is_break( &c8 , 1 ))
 425                 *__ctrlc = 1;
 426         }
 427
 428         // Acknowledge the interrupt
 429         HAL_INTERRUPT_ACKNOWLEDGE(chan->isr_vector);
 430         res = CYG_ISR_HANDLED;
 431     }
 432
 433     CYGARC_HAL_RESTORE_GP();
 434     return res;
 435 }
 436
 437 static void cyg_hal_plf_duart_init(void)
 438 {
 439     hal_virtual_comm_table_t* comm;
 440     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 441     int i;
 442
 443     CHECK_BOARD_VERSION_RET_VOID;
 444
 445     // Init channels
 446 #define NUMOF(x) (sizeof(x)/sizeof(x[0]))
 447     for (i = 0;  i < NUMOF(channels);  i++) {
 448         HAL_INTERRUPT_MASK(channels[i].isr_vector);
 449         init_duart_channel(&channels[i]);
 450         CYGACC_CALL_IF_SET_CONSOLE_COMM(i);
 451         comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 452         CYGACC_COMM_IF_CH_DATA_SET(*comm, &channels[i]);
 453         CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_duart_write);
 454         CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_duart_read);
 455         CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_duart_putc);
 456         CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_duart_getc);
 457         CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_duart_control);
 458         CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_duart_isr);
 459         CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_duart_getc_timeout);
 460     }
 461
 462     // Restore original console
 463     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 464 }
 465
 466 //=============================================================================
 467 // Compatibility with older stubs
 468 //=============================================================================
 469
 470 //=============================================================================
 471 // Compatibility with older stubs
 472 //=============================================================================
 473
 474 #ifndef CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 475
 476 #include <cyg/hal/hal_stub.h>           // cyg_hal_gdb_interrupt
 477
 478 #if (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 0)
 479 #define __BASE   CMA101_DUARTA
 480 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_A
 481 #elif (CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL == 1)
 482 #define __BASE   CMA101_DUARTB
 483 #define _INT     CYGNUM_HAL_INTERRUPT_SERIAL_B
 484 #endif
 485
 486 #ifdef __BASE
 487
 488 #ifdef CYGSEM_HAL_ROM_MONITOR
 489 #define CYG_HAL_STARTUP_ROM
 490 #define CYG_HAL_STARTUP_ROMRAM
 491 #undef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 492 #endif
 493
 494 #if (defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)) && !defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 495 #define HAL_DIAG_USES_HARDWARE
 496 #elif !defined(CYGDBG_HAL_DIAG_TO_DEBUG_CHAN)
 497 #define HAL_DIAG_USES_HARDWARE
 498 #elif CYGNUM_HAL_VIRTUAL_VECTOR_CONSOLE_CHANNEL != CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL
 499 #define HAL_DIAG_USES_HARDWARE
 500 #endif
 501
 502 static channel_data_t channel = {
 503     (uart_width*) _BASE, 0, 0
 504 };
 505
 506 #ifdef HAL_DIAG_USES_HARDWARE
 507
 508 void hal_diag_init(void)
 509 {
 510     static int init = 0;
 511     char *msg = "\n\rARM eCos\n\r";
 512     uart_width lcr;
 513
 514     if (init++) return;
 515
 516     init_duart_channel(&channel);
 517
 518     while (*msg) hal_diag_write_char(*msg++);
 519 }
 520
 521 #ifdef DEBUG_DIAG
 522 #if defined(CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS)
 523 #define DIAG_BUFSIZE 32
 524 #else
 525 #define DIAG_BUFSIZE 2048
 526 #endif
 527 static char diag_buffer[DIAG_BUFSIZE];
 528 static int diag_bp = 0;
 529 #endif
 530
 531 void hal_diag_write_char(char c)
 532 {
 533     uart_width lsr;
 534
 535     hal_diag_init();
 536
 537     cyg_hal_plf_duart_putc(&channel, c)
 538
 539 #ifdef DEBUG_DIAG
 540     diag_buffer[diag_bp++] = c;
 541     if (diag_bp == DIAG_BUFSIZE) {
 542         while (1) ;
 543         diag_bp = 0;
 544     }
 545 #endif
 546 }
 547
 548 void hal_diag_read_char(char *c)
 549 {
 550     *c = cyg_hal_plf_duart_getc(&channel);
 551 }
 552
 553 #else // HAL_DIAG relies on GDB
 554
 555 // Initialize diag port - assume GDB channel is already set up
 556 void hal_diag_init(void)
 557 {
 558     if (0) init_duart_channel(&channel); // avoid warning
 559 }
 560
 561 // Actually send character down the wire
 562 static void hal_diag_write_char_serial(char c)
 563 {
 564     cyg_hal_plf_duart_putc(&channel, c);
 565 }
 566
 567 static bool hal_diag_read_serial(char *c)
 568 {
 569     long timeout = 1000000000;  // A long time...
 570
 571     while (!cyg_hal_plf_duart_getc_nonblock(&channel, c))
 572         if (0 == --timeout) return false;
 573
 574     return true;
 575 }
 576
 577 void hal_diag_read_char(char *c)
 578 {
 579     while (!hal_diag_read_serial(c)) ;
 580 }
 581
 582 void hal_diag_write_char(char c)
 583 {
 584     static char line[100];
 585     static int pos = 0;
 586
 587     // No need to send CRs
 588     if (c == '\r') return;
 589
 590     line[pos++] = c;
 591
 592     if (c == '\n' || pos == sizeof(line)) {
 593         CYG_INTERRUPT_STATE old;
 594
 595         // Disable interrupts. This prevents GDB trying to interrupt us
 596         // while we are in the middle of sending a packet. The serial
 597         // receive interrupt will be seen when we re-enable interrupts
 598         // later.
 599
 600 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 601         CYG_HAL_GDB_ENTER_CRITICAL_IO_REGION(old);
 602 #else
 603         HAL_DISABLE_INTERRUPTS(old);
 604 #endif
 605
 606         while (1) {
 607             static char hex[] = "0123456789ABCDEF";
 608             cyg_uint8 csum = 0;
 609             int i;
 610             char c1;
 611
 612             hal_diag_write_char_serial('$');
 613             hal_diag_write_char_serial('O');
 614             csum += 'O';
 615             for (i = 0; i < pos; i++) {
 616                 char ch = line[i];
 617                 char h = hex[(ch>>4)&0xF];
 618                 char l = hex[ch&0xF];
 619                 hal_diag_write_char_serial(h);
 620                 hal_diag_write_char_serial(l);
 621                 csum += h;
 622                 csum += l;
 623             }
 624             hal_diag_write_char_serial('#');
 625             hal_diag_write_char_serial(hex[(csum>>4)&0xF]);
 626             hal_diag_write_char_serial(hex[csum&0xF]);
 627
 628             // Wait for the ACK character '+' from GDB here and handle
 629             // receiving a ^C instead.  This is the reason for this clause
 630             // being a loop.
 631             if (!hal_diag_read_serial(&c1))
 632                 continue;   // No response - try sending packet again
 633
 634             if ( c1 == '+' )
 635                 break;          // a good acknowledge
 636
 637 #ifdef CYGDBG_HAL_DEBUG_GDB_BREAK_SUPPORT
 638             cyg_drv_interrupt_acknowledge(CYG_DEV_SERIAL_INT);
 639             if ( c1 == 3 ) {
 640                 // Ctrl-C: breakpoint.
 641                 cyg_hal_gdb_interrupt (__builtin_return_address(0));
 642                 break;
 643             }
 644 #endif
 645             // otherwise, loop round again
 646         }
 647
 648         pos = 0;
 649
 650         // And re-enable interrupts
 651 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
 652         CYG_HAL_GDB_LEAVE_CRITICAL_IO_REGION(old);
 653 #else
 654         HAL_RESTORE_INTERRUPTS(old);
 655 #endif
 656
 657     }
 658 }
 659 #endif
 660
 661 #endif // __BASE
 662
 663 #endif // CYGSEM_HAL_VIRTUAL_VECTOR_DIAG
 664
 665 /*---------------------------------------------------------------------------*/