1 //==========================================================================
5 // HAL misc board support code
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================*/
42 #include <pkgconf/hal.h>
43 #include <pkgconf/system.h>
44 #include CYGBLD_HAL_PLATFORM_H
46 #include <cyg/infra/cyg_type.h> // base types
47 #include <cyg/infra/cyg_trac.h> // tracing macros
48 #include <cyg/infra/cyg_ass.h> // assertion macros
50 #include <cyg/hal/hal_io.h> // IO macros
51 #include <cyg/hal/hal_arch.h> // Register state info
52 #include <cyg/hal/hal_diag.h>
53 #include <cyg/hal/hal_intr.h> // Interrupt names
54 #include <cyg/hal/hal_cache.h>
55 #include <cyg/hal/hal_soc.h> // Hardware definitions
56 #include <cyg/hal/fsl_board.h> // Platform specifics
58 #include <cyg/infra/diag.h> // diag_printf
60 // All the MM table layout is here:
61 #include <cyg/hal/hal_mm.h>
63 externC void* memset(void *, int, size_t);
65 void hal_mmu_init(void)
67 unsigned long ttb_base = RAM_BANK0_BASE + 0x4000;
71 * Set the TTB register
73 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
76 * Set the Domain Access Control Register
78 i = ARM_ACCESS_DACR_DEFAULT;
79 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
82 * First clear all TT entries - ie Set them to Faulting
84 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
86 /* Actual Virtual Size Attributes Function */
87 /* Base Base MB cached? buffered? access permissions */
88 /* xxx00000 xxx00000 */
89 X_ARM_MMU_SECTION(0x000, 0xF00, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* ROM */
90 X_ARM_MMU_SECTION(0x300, 0x300, 0x1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* L2CC */
91 X_ARM_MMU_SECTION(0x43F, 0x43F, 0x3C1, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Internal Regsisters upto SDRAM*/
92 X_ARM_MMU_SECTION(0x900, 0x000, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
93 X_ARM_MMU_SECTION(0x900, 0x900, 0x40, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* SDRAM */
94 X_ARM_MMU_SECTION(0xA00, 0xA00, 0x20, ARM_CACHEABLE, ARM_BUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* Flash */
95 X_ARM_MMU_SECTION(0xB00, 0xB00, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
96 X_ARM_MMU_SECTION(0xB40, 0xB40, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* External I/O */
97 X_ARM_MMU_SECTION(0xB80, 0xB80, 0x10, ARM_UNCACHEABLE, ARM_UNBUFFERABLE, ARM_ACCESS_PERM_RW_RW); /* EIM control*/
101 // Platform specific initialization
104 void plf_hardware_init(void)
108 #include CYGHWR_MEMORY_LAYOUT_H
110 typedef void code_fun(void);
112 void board_program_new_stack(void *func)
114 register CYG_ADDRESS stack_ptr asm("sp");
115 register CYG_ADDRESS old_stack asm("r4");
116 register code_fun *new_func asm("r0");
117 old_stack = stack_ptr;
118 stack_ptr = CYGMEM_REGION_ram + CYGMEM_REGION_ram_SIZE - sizeof(CYG_ADDRESS);
119 new_func = (code_fun*)func;
121 stack_ptr = old_stack;
124 // ------------------------------------------------------------------------