1 #ifndef CYGONCE_HAL_SA11X0_PLATFORM_PLF_MMAP_H
2 #define CYGONCE_HAL_SA11X0_PLATFORM_PLF_MMAP_H
3 /*=============================================================================
7 // Platform specific memory map support
9 //=============================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
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21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
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32 // License. However the source code for this file must still be made available
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
48 // Purpose: Intel SA11x0 series platform-specific memory mapping macros
49 // Description: Macros to convert a cached, virtual address to
50 // 1) an uncached adddress for the same memory (if available)
51 // 2) the equivalent physical address for giving to external
52 // hardware eg. DMA engines.
54 // NB: this mapping is expressed here statically, independent
55 // of the actual mapping installed in the MMAP table. So if
56 // someone changes that, or its initialisation is changed,
57 // then this module must change. This is intended to be
58 // efficient at a cost of generality. It is also intended to
59 // be called with constants (such as &my_struct) as input
60 // args, so that all the work can be done at compile time,
61 // with optimization on.
63 // Usage: #include <cyg/hal/hal_cache.h>
64 // (which includes this file itself)
66 //####DESCRIPTIONEND####
68 //===========================================================================*/
70 #include <cyg/hal/hal_misc.h>
72 // Get the pagesize for a particular virtual address:
74 // This does not depend on the vaddr.
75 #define HAL_MM_PAGESIZE( vaddr, pagesize ) CYG_MACRO_START \
79 // Get the physical address from a virtual address:
81 // Only RAM and ROM are mapped; we just pass through all other values,
82 // rather than detecting nonexistent areas here.
84 #define HAL_VIRT_TO_PHYS_ADDRESS( vaddr, paddr ) CYG_MACRO_START \
85 cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
86 if ( 4 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 0 from 0-4Mb */ \
87 _v_ += 0xc00u * SZ_1M; \
88 if ( 8 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 1 from 4-8Mb */ \
89 _v_ += (0xc80u * SZ_1M) - (4 * SZ_1M); \
90 if ( 12 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 2 from 8-12Mb */ \
91 _v_ += (0xd00u * SZ_1M) - (8 * SZ_1M); \
92 if ( 16 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 3 from 12-16M */ \
93 _v_ += (0xd80u * SZ_1M) - (12 * SZ_1M); \
94 else if ( 0x400u * SZ_1M > _v_ ) /* Space between RAM and mapped ROM */\
96 else if ( 0x401u * SZ_1M > _v_ ) /* Mapped boot ROM size 1Mb */ \
97 _v_ -= 0x400u * SZ_1M; \
98 else /* Rest of it */ \
103 // Get the virtual address for a physical address:
105 // Only RAM and ROM are mapped; we just pass through all other values,
106 // rather than detecting nonexistent areas here.
108 #define HAL_PHYS_TO_VIRT_ADDRESS( paddr, vaddr ) CYG_MACRO_START \
109 cyg_uint32 _p_ = (cyg_uint32)(paddr); \
110 if ( 1 * SZ_1M > _p_ ) /* 1Mb Boot ROM mapped to 0x400Mb */ \
111 _p_ += 0x400u * SZ_1M; \
112 else if ( 0xc00u * SZ_1M > _p_ ) /* Space between ROM and SDRAM */ \
114 else if ( 0xc04u * SZ_1M > _p_ ) /* Raw RAM bank 0, 4Mb at 0xc00 */ \
115 _p_ -= 0xc00u * SZ_1M; \
116 else if ( 0xc80u * SZ_1M > _p_ ) /* Space between SDRAM banks */ \
118 else if ( 0xc84u * SZ_1M > _p_ ) /* Raw RAM bank 1, 4Mb at 0xc80 */ \
119 _p_ -= (0xc80u * SZ_1M) - (4 * SZ_1M); \
120 else if ( 0xd00u * SZ_1M > _p_ ) /* Space between SDRAM banks */ \
122 else if ( 0xd04u * SZ_1M > _p_ ) /* Raw RAM bank 2, 4Mb at 0xd00 */ \
123 _p_ -= (0xd00u * SZ_1M) - (8 * SZ_1M); \
124 else if ( 0xd80u * SZ_1M > _p_ ) /* Space between SDRAM banks */ \
126 else if ( 0xd84u * SZ_1M > _p_ ) /* Raw RAM bank 3, 4Mb at 0xd80 */ \
127 _p_ -= (0xd80u * SZ_1M) - (12 * SZ_1M); \
128 else /* Rest of it */ \
133 // Get a non-cacheable address for accessing the same store as a virtual
134 // (assumed cachable) address:
136 // Only RAM is mapped: ROM is only available cachable, everything else is
137 // not cachable anyway.
139 #define HAL_VIRT_TO_UNCACHED_ADDRESS( vaddr, uaddr ) CYG_MACRO_START \
140 cyg_uint32 _v_ = (cyg_uint32)(vaddr); \
141 if ( 4 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 0 from 0-4Mb */ \
142 _v_ += 0xc00u * SZ_1M; \
143 if ( 8 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 1 from 4-8Mb */ \
144 _v_ += (0xc80u * SZ_1M) - (4 * SZ_1M); \
145 if ( 12 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 2 from 8-12Mb */ \
146 _v_ += (0xd00u * SZ_1M) - (8 * SZ_1M); \
147 if ( 16 * SZ_1M > _v_ ) /* 4Mb of SDRAM Bank 3 from 12-16M */ \
148 _v_ += (0xd80u * SZ_1M) - (12 * SZ_1M); \
149 else /* Everything else is already uncacheable or is ROM */ \
154 //---------------------------------------------------------------------------
155 #endif // CYGONCE_HAL_SA11X0_PLATFORM_PLF_MMAP_H