1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: gthomas
49 // Purpose: Intel SA1110/Assabet platform specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant (SA11x0) specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_sa11x0.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/cerf.h> // Platform specific hardware definitions
65 #if defined(CYG_HAL_STARTUP_ROM)
66 #define PLATFORM_SETUP1 _platform_setup1
67 #define CYGHWR_HAL_ARM_HAS_MMU
69 #if (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 59000)
70 #define SA11X0_PLL_CLOCK 0x0
71 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 73700)
72 #define SA11X0_PLL_CLOCK 0x1
73 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 88500)
74 #define SA11X0_PLL_CLOCK 0x2
75 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 103200)
76 #define SA11X0_PLL_CLOCK 0x3
77 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 118000)
78 #define SA11X0_PLL_CLOCK 0x4
79 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 132700)
80 #define SA11X0_PLL_CLOCK 0x5
81 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 147500)
82 #define SA11X0_PLL_CLOCK 0x6
83 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 162200)
84 #define SA11X0_PLL_CLOCK 0x7
85 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 176900)
86 #define SA11X0_PLL_CLOCK 0x8
87 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 191700)
88 #define SA11X0_PLL_CLOCK 0x9
89 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 206400)
90 #define SA11X0_PLL_CLOCK 0xA
91 #elif (CYGHWR_HAL_ARM_SA11X0_PROCESSOR_CLOCK == 221200)
92 #define SA11X0_PLL_CLOCK 0xB
94 #error Invalid processor clock speed
97 #define CAS0_WAVEFORM_VALUE 0xAAAAAA9F
98 #define CAS1_WAVEFORM_VALUE 0xAAAAAAAA
99 #define CAS2_WAVEFORM_VALUE 0xAAAAAAAA
101 #define MSC0VALUE 0xFFFCFFFC
102 #define MSC1VALUE 0xFFFFFFFF
103 #define MSC2VALUE 0xFFFFFFFF
105 #define DRAM_CONFIG_VALUE 0x72547254
106 #define RFSH_CONFIG_VALUE 0x003002D1
108 // Macros that handle the red debug LED wired to GPIO-1
111 ldr r1,=SA11X0_GPIO_PIN_OUTPUT_SET
122 ldr r1,=SA11X0_GPIO_PIN_OUTPUT_CLEAR
132 // This macro represents the initial startup code for the platform
133 .macro _platform_setup1
135 // Disable all interrupts (ICMR not specified on power-up)
140 // Initialize the CPU.
141 mov r0, #0x0 // Get a zero to turn things off
142 mcr p15, 0, r0, c1, c0, 0 // MMU off
143 mcr p15, 0, r0, c8, c7, 0 // Flush TLB
144 mcr p15, 0, r0, c7, c7, 0 // Flush caches
150 // Disable IRQs and FIQs
151 mov r0, #(CPSR_IRQ_DISABLE | \
153 CPSR_SUPERVISOR_MODE)
156 // Set up GPIOs (LED1 off)
157 ldr r1,=SA11X0_GPIO_PIN_DIRECTION
158 ldr r2,=0x0320000f // Set LT1348,DREN,RXEN,CF and LEDs to be output
160 ldr r3,=SA11X0_GPIO_PIN_OUTPUT_SET
161 ldr r2,=0x0300000f // Set the LT1348,DREN,RXEN and LEDs to 1.
163 ldr r3,=SA11X0_GPIO_PIN_OUTPUT_CLEAR
164 ldr r2,=0x0020000f // Set CF reset,LEDS OFF
170 // Disable clock switching
172 SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
173 SA11X0_DISABLE_CLOCK_SWITCHING_RM,\
174 SA11X0_DISABLE_CLOCK_SWITCHING_OPCODE
176 // Set up processor clock
177 ldr r1,=SA11X0_PWR_MGR_PLL_CONFIG
178 ldr r2,=SA11X0_PLL_CLOCK
181 // Turn clock switching back on
183 SA11X0_TEST_CLOCK_AND_IDLE_REGISTER,\
184 SA11X0_ENABLE_CLOCK_SWITCHING_RM,\
185 SA11X0_ENABLE_CLOCK_SWITCHING_OPCODE
189 // Let the PLL settle down
198 // Initialize DRAM controller
200 ldr r2,=__exception_handlers
202 ldr r2,[r1],#4 // First control register
205 ldr r2,[r1],#4 // Next control register
213 ldr r1,=SA1110_GPCLK_CONTROL_0
214 ldr r2,=SA1110_GPCLK_SUS_UART
217 // Release DRAM hold (set by RESET)
218 ldr r1,=SA11X0_PWR_MGR_SLEEP_STATUS
219 ldr r2,=SA11X0_DRAM_CONTROL_HOLD
222 // Perform 8 reads from unmapped/unenabled DRAM
223 ldr r1,=SA11X0_RAM_BANK0_BASE
233 // Enable DRAM bank 0
234 ldr r1,=SA11X0_DRAM_CONFIGURATION
235 ldr r2,=DRAM_CONFIG_VALUE
240 // Wait for the DRAM to come up.
250 // DRAM controller initialization
252 .word SA11X0_DRAM0_CAS_0, CAS0_WAVEFORM_VALUE
253 .word SA11X0_DRAM0_CAS_1, CAS1_WAVEFORM_VALUE
254 .word SA11X0_DRAM0_CAS_2, CAS2_WAVEFORM_VALUE
255 .word SA11X0_DRAM2_CAS_0, CAS0_WAVEFORM_VALUE
256 .word SA11X0_DRAM2_CAS_1, CAS1_WAVEFORM_VALUE
257 .word SA11X0_DRAM2_CAS_2, CAS2_WAVEFORM_VALUE
258 .word SA11X0_REFRESH_CONFIGURATION, RFSH_CONFIG_VALUE
259 .word SA11X0_DRAM_CONFIGURATION, DRAM_CONFIG_VALUE
260 .word SA11X0_STATIC_CONTROL_0, MSC0VALUE
261 .word SA11X0_STATIC_CONTROL_1, MSC1VALUE
262 .word SA11X0_STATIC_CONTROL_2, MSC2VALUE
266 // Wakeup from deep sleep mode
267 ldr r1,=SA11X0_RESET_STATUS
269 cmp r2,#SA11X0_SLEEP_MODE_RESET
271 ldr r1,=SA11X0_PWR_MGR_SCRATCHPAD
277 // Release peripheral hold (set by RESET)
278 ldr r1,=SA11X0_PWR_MGR_SLEEP_STATUS
279 ldr r2,=SA11X0_PERIPHERAL_CONTROL_HOLD
282 // Set up a stack [for calling C code]
283 ldr r1,=__startup_stack
284 ldr r2,=SA11X0_RAM_BANK0_BASE
295 ldr r1,=MMU_Control_Init|MMU_Control_M
296 mcr MMU_CP,0,r1,MMU_Control,c0
297 mov pc,r2 /* Change address spaces */
306 // Save shadow copy of BCR, also hardware configuration
311 #else // defined(CYG_HAL_STARTUP_ROM)
312 #define PLATFORM_SETUP1
315 #define PLATFORM_VECTORS _platform_vectors
316 .macro _platform_vectors
318 _cerf_BCR: .long 0 // Board Control register shadow
321 /*---------------------------------------------------------------------------*/
322 /* end of hal_platform_setup.h */
323 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */