4 //=============================================================================
8 // Platform specific support (register layout, etc)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2002 Gary Thomas
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
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23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
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28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
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38 // this file might be covered by the GNU General Public License.
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41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //=============================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: gthomas, richard.panton@3glab.com
50 // Purpose: Intel SA1110/iPAQ platform specific support routines
52 // Usage: #include <cyg/hal/ipaq.h>
54 //####DESCRIPTIONEND####
56 //=============================================================================
62 // Note: This register is write-only. Thus a shadow copy is provided so that
63 // it may be safely updated/shared by multiple threads.
65 extern unsigned long _ipaq_EGPIO; // Shadow copy
67 extern unsigned short _ipaq_LCD_params[(4*2)+1]; // Various LCD parameters
69 extern void ipaq_EGPIO(unsigned long mask, unsigned long value);
74 // Signal assertion levels
76 #define _LOGIC_ONE(m) (m & 0xFFFF)
77 #define _LOGIC_ZERO(m) (m & 0x0000)
80 // iPAQ Extended GPIO definitions
82 #define SA1110_EGPIO REG16_PTR(0x49000000)
83 #define SA1110_EIO_MIN 0x0080
85 #define SA1110_EIO_VPP 0x0001
86 # define SA1110_EIO_VPP_OFF _LOGIC_ZERO(SA1110_EIO_VPP)
87 # define SA1110_EIO_VPP_ON _LOGIC_ONE(SA1110_EIO_VPP)
88 #define SA1110_EIO_CF_RESET 0x0002
89 # define SA1110_EIO_CF_RESET_DISABLE _LOGIC_ZERO(SA1110_EIO_CF_RESET)
90 # define SA1110_EIO_CF_RESET_ENABLE _LOGIC_ONE(SA1110_EIO_CF_RESET)
91 #define SA1110_EIO_OPT_RESET 0x0004
92 # define SA1110_EIO_OPT_RESET_DISABLE _LOGIC_ZERO(SA1110_EIO_OPT_RESET)
93 # define SA1110_EIO_OPT_RESET_ENABLE _LOGIC_ONE(SA1110_EIO_OPT_RESET)
94 #define SA1110_EIO_CODEC_RESET 0x0008 // Active LOW
95 # define SA1110_EIO_CODEC_RESET_DISABLE _LOGIC_ONE(SA1110_EIO_CODEC_RESET)
96 # define SA1110_EIO_CODEC_RESET_ENABLE _LOGIC_ZERO(SA1110_EIO_CODEC_RESET)
97 #define SA1110_EIO_OPT_PWR 0x0010
98 # define SA1110_EIO_OPT_PWR_OFF _LOGIC_ZERO(SA1110_EIO_OPT_PWR)
99 # define SA1110_EIO_OPT_PWR_ON _LOGIC_ONE(SA1110_EIO_OPT_PWR)
100 #define SA1110_EIO_OPT 0x0020
101 # define SA1110_EIO_OPT_OFF _LOGIC_ZERO(SA1110_EIO_OPT)
102 # define SA1110_EIO_OPT_ON _LOGIC_ONE(SA1110_EIO_OPT)
103 #define SA1110_EIO_LCD_3V3 0x0040
104 # define SA1110_EIO_LCD_3V3_OFF _LOGIC_ZERO(SA1110_EIO_LCD_3V3)
105 # define SA1110_EIO_LCD_3V3_ON _LOGIC_ONE(SA1110_EIO_LCD_3V3)
106 #define SA1110_EIO_RS232 0x0080
107 # define SA1110_EIO_RS232_OFF _LOGIC_ZERO(SA1110_EIO_RS232)
108 # define SA1110_EIO_RS232_ON _LOGIC_ONE(SA1110_EIO_RS232)
109 #define SA1110_EIO_LCD_CTRL 0x0100
110 # define SA1110_EIO_LCD_CTRL_OFF _LOGIC_ZERO(SA1110_EIO_LCD_CTRL)
111 # define SA1110_EIO_LCD_CTRL_ON _LOGIC_ONE(SA1110_EIO_LCD_CTRL)
112 #define SA1110_EIO_IR 0x0200
113 # define SA1110_EIO_IR_OFF _LOGIC_ZERO(SA1110_EIO_IR)
114 # define SA1110_EIO_IR_ON _LOGIC_ONE(SA1110_EIO_IR)
115 #define SA1110_EIO_AMP 0x0400
116 # define SA1110_EIO_AMP_OFF _LOGIC_ZERO(SA1110_EIO_AMP)
117 # define SA1110_EIO_AMP_ON _LOGIC_ONE(SA1110_EIO_AMP)
118 #define SA1110_EIO_AUDIO 0x0800
119 # define SA1110_EIO_AUDIO_OFF _LOGIC_ZERO(SA1110_EIO_AUDIO)
120 # define SA1110_EIO_AUDIO_ON _LOGIC_ONE(SA1110_EIO_AUDIO)
121 #define SA1110_EIO_MUTE 0x1000
122 # define SA1110_EIO_MUTE_OFF _LOGIC_ZERO(SA1110_EIO_MUTE)
123 # define SA1110_EIO_MUTE_ON _LOGIC_ONE(SA1110_EIO_MUTE)
124 #define SA1110_EIO_IR_FSEL 0x2000
125 # define SA1110_EIO_SIR _LOGIC_ZERO(SA1110_EIO_IR_FSEL)
126 # define SA1110_EIO_FIR _LOGIC_ONE(SA1110_EIO_IR_FSEL)
127 #define SA1110_EIO_LCD_5V 0x4000
128 # define SA1110_EIO_LCD_5V_OFF _LOGIC_ZERO(SA1110_EIO_LCD_5V)
129 # define SA1110_EIO_LCD_5V_ON _LOGIC_ONE(SA1110_EIO_LCD_5V)
130 #define SA1110_EIO_LCD_VDD 0x8000
131 # define SA1110_EIO_LCD_VDD_OFF _LOGIC_ZERO(SA1110_EIO_LCD_VDD)
132 # define SA1110_EIO_LCD_VDD_ON _LOGIC_ONE(SA1110_EIO_LCD_VDD)
135 // Special purpose GPIO interrupt mappings
137 #define SA1110_CF_IRQ CYGNUM_HAL_INTERRUPT_GPIO21
138 #define SA1110_CF_DETECT CYGNUM_HAL_INTERRUPT_GPIO17
143 #define SA1110_GPIO_CF_DETECT 0x00020000 // 0 = Compact Flash detect
144 #define SA1110_GPIO_CF_PRESENT _LOGIC_ZERO(SA1110_GPIO_CF_DETECT)
145 #define SA1110_GPIO_CF_ABSENT _LOGIC_ONE(SA1110_GPIO_CF_DETECT)
146 #define SA1110_GPIO_CF2_DETECT 0x00000200 // 0 = Second slot on 2-slot sleeve
147 #define SA1110_GPIO_CF2_PRESENT _LOGIC_ZERO(SA1110_GPIO_CF2_DETECT)
148 #define SA1110_GPIO_CF2_ABSENT _LOGIC_ONE(SA1110_GPIO_CF2_DETECT)
151 // PCMCIA controller in external sleeve
153 #define IPAQ_CF_CTRL 0x1A000000 // Slot 0 (same as single slot)
154 #define IPAQ_CF2_CTRL 0x19000000 // Slot 1
155 #define IPAQ_CF_CTRL_V5 0x0001 // 5v power enable
156 #define IPAQ_CF_CTRL_V5_ENABLE _LOGIC_ZERO(IPAQ_CF_CTRL_V5)
157 #define IPAQ_CF_CTRL_V5_DISABLE _LOGIC_ONE(IPAQ_CF_CTRL_V5)
158 #define IPAQ_CF_CTRL_V3 0x0002 // 3v power enable
159 #define IPAQ_CF_CTRL_V3_ENABLE _LOGIC_ZERO(IPAQ_CF_CTRL_V3)
160 #define IPAQ_CF_CTRL_V3_DISABLE _LOGIC_ONE(IPAQ_CF_CTRL_V3)
161 #define IPAQ_CF_CTRL_VCC 0x0004 // Vcc power enable
162 #define IPAQ_CF_CTRL_V12 0x0008 // 12v power enable
163 #define IPAQ_CF_CTRL_RESET 0x0010 // Reset card
164 #define IPAQ_CF_CTRL_RESET_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_RESET)
165 #define IPAQ_CF_CTRL_RESET_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_RESET)
166 #define IPAQ_CF_CTRL_APOE 0x0020 // Auto power off
167 #define IPAQ_CF_CTRL_APOE_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_APOE)
168 #define IPAQ_CF_CTRL_APOE_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_APOE)
169 #define IPAQ_CF_CTRL_CFE 0x0040 // Compact Flash [addressing] enable
170 #define IPAQ_CF_CTRL_SOE 0x0080 // Enable signal outputs
171 #define IPAQ_CF_CTRL_SOE_ENABLE _LOGIC_ONE(IPAQ_CF_CTRL_SOE)
172 #define IPAQ_CF_CTRL_SOE_DISABLE _LOGIC_ZERO(IPAQ_CF_CTRL_SOE)
173 #define IPAQ_CF_CTRL_SSP 0x0100 // Slot polarity; slot0=0, slot1=1
179 #define SA1110_LCCR0 SA11X0_REGISTER(0x30100000)
180 #define SA1110_LCSR SA11X0_REGISTER(0x30100004)
181 #define SA1110_DBAR1 SA11X0_REGISTER(0x30100010)
182 #define SA1110_DCAR1 SA11X0_REGISTER(0x30100014)
183 #define SA1110_DBAR2 SA11X0_REGISTER(0x30100018)
184 #define SA1110_DCAR2 SA11X0_REGISTER(0x3010001C)
185 #define SA1110_LCCR1 SA11X0_REGISTER(0x30100020)
186 #define SA1110_LCCR2 SA11X0_REGISTER(0x30100024)
187 #define SA1110_LCCR3 SA11X0_REGISTER(0x30100028)
190 #endif /* CYGONCE_IPAQ_H */