1 //==========================================================================
5 // HAL PCI board support code for Intel XScale GRG
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002, 2003 Red Hat, Inc.
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
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37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: msalter
46 // Purpose: HAL PCI board support
47 // Description: Implementations of HAL board interfaces
49 //####DESCRIPTIONEND####
51 //========================================================================*/
52 #include <pkgconf/hal.h>
53 #include <pkgconf/system.h>
54 #include CYGBLD_HAL_PLATFORM_H
58 #include <cyg/infra/cyg_type.h> // base types
59 #include <cyg/infra/cyg_trac.h> // tracing macros
60 #include <cyg/infra/cyg_ass.h> // assertion macros
62 #include <cyg/hal/hal_io.h> // IO macros
63 #include <cyg/hal/hal_if.h> // calling interface API
64 #include <cyg/hal/hal_arch.h> // Register state info
65 #include <cyg/hal/hal_diag.h>
66 #include <cyg/hal/hal_intr.h> // Interrupt names
67 #include <cyg/hal/hal_cache.h>
68 #include <cyg/io/pci_hw.h>
69 #include <cyg/io/pci.h>
72 #define IXP425_PCI_MAX_DEV 4
73 #define IXP425_PCI_IRQ_LINES 4
76 #define PCI_CLK_GPIO 14 // CLK0
77 #define PCI_RESET_GPIO 12
78 #define PCI_INTA_GPIO 11
80 #define INTA CYGNUM_HAL_INTERRUPT_GPIO11
83 cyg_hal_plf_pci_translate_interrupt(cyg_uint32 bus, cyg_uint32 devfn,
84 CYG_ADDRWORD *vec, cyg_bool *valid)
91 #define HAL_PCI_CLOCK_ENABLE() \
92 *IXP425_GPCLKR |= GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock
94 #define HAL_PCI_CLOCK_DISABLE() \
95 *IXP425_GPCLKR &= ~GPCLKR_CLK0_ENABLE; // GPIO(0) used for PCI clock
97 #define HAL_PCI_CLOCK_CONFIG() \
98 *IXP425_GPCLKR |= GPCLKR_CLK0_PCLK2;
100 #define HAL_PCI_RESET_ASSERT() \
101 HAL_GPIO_OUTPUT_CLEAR(PCI_RESET_GPIO);
103 #define HAL_PCI_RESET_DEASSERT() \
104 HAL_GPIO_OUTPUT_SET(PCI_RESET_GPIO);
107 hal_plf_pci_init(void)
109 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
110 HAL_PCI_RESET_ASSERT();
111 HAL_PCI_CLOCK_DISABLE();
113 // Set GPIO line direction
114 HAL_GPIO_OUTPUT_ENABLE(PCI_CLK_GPIO);
115 HAL_GPIO_OUTPUT_ENABLE(PCI_RESET_GPIO);
116 HAL_GPIO_OUTPUT_DISABLE(PCI_INTA_GPIO);
118 // configure PCI interrupt lines for active low irq
119 HAL_INTERRUPT_CONFIGURE(INTA, 1, 0);
121 // wait 1ms to satisfy "minimum reset assertion time" of the PCI spec.
123 HAL_PCI_CLOCK_CONFIG();
124 HAL_PCI_CLOCK_ENABLE();
126 // wait 100us to satisfy "minimum reset assertion time from clock stable"
127 // requirement of the PCI spec.
129 HAL_PCI_RESET_DEASSERT();
133 #endif // CYGPKG_IO_PCI