1 #ifndef CYGONCE_PLF_IO_H
2 #define CYGONCE_PLF_IO_H
4 //=============================================================================
8 // Platform specific IO support
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Intel IQ80321 PCI IO support macros
51 // Usage: #include <cyg/hal/plf_io.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include <pkgconf/hal.h>
58 #include <cyg/hal/hal_io.h> // IO macros
59 #include <cyg/hal/iq80321.h>
60 #include CYGBLD_HAL_PLF_INTS_H
62 // Initialize the PCI bus.
63 externC void cyg_hal_plf_pci_init(void);
64 #define HAL_PCI_INIT() cyg_hal_plf_pci_init()
66 //-----------------------------------------------------------------------------
69 #define _PCI_MEM_BASE 0x80000000
70 #define _PCI_MEM_DAC_BASE 0x00000000
71 #define _PCI_IO_BASE 0x90000000
72 #define _PCI_MEM_LIMIT 0x83ffffff
73 #define _PCI_IO_LIMIT 0x9000ffff
75 extern cyg_uint32 hal_pci_alloc_base_memory;
76 extern cyg_uint32 hal_pci_alloc_base_io;
78 extern cyg_uint32 hal_pci_physical_memory_base;
79 extern cyg_uint32 hal_pci_physical_io_base;
81 extern cyg_uint32 hal_pci_inbound_window_base;
82 extern cyg_uint32 hal_pci_inbound_window_mask;
84 #define HAL_PCI_PHYSICAL_MEMORY_BASE hal_pci_physical_memory_base
85 #define HAL_PCI_PHYSICAL_IO_BASE hal_pci_physical_io_base
87 // Map PCI device resources starting from these addresses in PCI space.
88 #define HAL_PCI_ALLOC_BASE_MEMORY hal_pci_alloc_base_memory
89 #define HAL_PCI_ALLOC_BASE_IO hal_pci_alloc_base_io
91 #ifdef CYGSEM_HAL_ARM_IQ80321_FAB_C
92 #define __INTA_ROUTING CYGNUM_HAL_INTERRUPT_XINT0
93 #define __INTB_ROUTING CYGNUM_HAL_INTERRUPT_XINT1
101 #define __INTA_ROUTING CYGNUM_HAL_INTERRUPT_XINT2
102 #define __INTB_ROUTING CYGNUM_HAL_INTERRUPT_XINT3
108 #define __SLOT_PRIV 6
111 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
112 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
113 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
115 cyg_uint32 __dev = CYG_PCI_DEV_GET_DEV(__devfn); \
116 cyg_uint32 __fn = CYG_PCI_DEV_GET_FN(__devfn); \
117 cyg_uint32 __xbus = ((*ATU_PCIXSR >> 8) & 0xff); \
118 if (__xbus == 0xff) __xbus = 0; \
120 if (__fn==0 && (__dev==__NIC_PUB || __dev==__NIC_PRIV) && __bus==__xbus) { \
121 __vec = CYGNUM_HAL_INTERRUPT_ETHERNET; \
125 HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req); \
128 __vec=CYGNUM_HAL_INTERRUPT_XINT0; __valid=true; break; \
130 __vec=CYGNUM_HAL_INTERRUPT_XINT1; __valid=true; break; \
135 // SDRAM is aliased as uncached memory for drivers.
136 #ifdef CYG_HAL_MEMORY_MAP_NORMAL
137 #define CYGARC_UNCACHED_ADDRESS(_x_) \
138 (((((unsigned long)(_x_)) >> 29)==0x0) ? (((unsigned long)(_x_))|0xC0000000) : (_x_))
140 #define CYGARC_UNCACHED_ADDRESS(_x_) \
141 (((((unsigned long)(_x_)) >> 29)==0x5) ? (((unsigned long)(_x_))+0x20000000) : (_x_))
144 #define CYGARC_VIRT_TO_BUS(_x_) \
145 (((unsigned long)(_x_) & 0x1fffffff) | hal_pci_inbound_window_base)
146 #define CYGARC_BUS_TO_VIRT(_x_) \
147 (((unsigned long)(_x_) & hal_pci_inbound_window_mask) | 0xC0000000)
150 static inline unsigned cygarc_physical_address(unsigned va)
152 unsigned *ram_mmutab = (unsigned *)(SDRAM_BASE | 0x4000);
155 pte = ram_mmutab[va >> 20];
157 return (pte & 0xfff00000) | (va & 0xfffff);
160 #define CYGARC_PHYSICAL_ADDRESS(_x_) cygarc_physical_address(_x_)
162 #ifdef CYG_HAL_MEMORY_MAP_NORMAL
163 static inline unsigned cygarc_virtual_address(unsigned pa)
165 if (0xa0000000 <= pa && pa < 0xc0000000)
166 return pa - 0xa0000000;
168 return pa + 0x20000000;
172 #define CYGARC_VIRTUAL_ADDRESS(_x_) cygarc_virtual_address(_x_)
174 #define CYGARC_VIRTUAL_ADDRESS(_x_) (_x_)
179 //-----------------------------------------------------------------------------
181 #endif // CYGONCE_PLF_IO_H