1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: msalter
49 // Purpose: Intel XScale IXPD specific support routines
51 // Usage: #include <cyg/hal/hal_platform_setup.h>
52 // Only used by "vectors.S"
54 //####DESCRIPTIONEND####
56 //===========================================================================*/
58 #include <pkgconf/system.h> // System-wide configuration info
59 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
60 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
61 #include <cyg/hal/hal_ixp425.h> // Variant specific hardware definitions
62 #include <cyg/hal/hal_mmu.h> // MMU definitions
63 #include <cyg/hal/hal_mm.h> // more MMU definitions
64 #include <cyg/hal/ixdp425.h> // Platform specific hardware definitions
66 // ------------------------------------------------------------------------
67 // Convenience macros for setting up page table
69 .macro IXP_MAP_SDRAM va, c, b, x, p
70 XSCALE_MMU_SECTION SDRAM_PHYS_BASE>>20, \va>>20, SDRAM_SIZE>>20, \c, \b, 3, \x, \p
73 .macro IXP_MAP_EXP_V n, va, sz, c, b, x, p
74 XSCALE_MMU_SECTION (0x500 + ((IXP425_EXP_CS_SIZE * \n) >> 20)), \va>>20, \sz>>20, \c, \b, 3, \x, \p
77 .macro IXP_MAP_EXP n, sz, c, b, x, p
78 IXP_MAP_EXP_V \n, (0x50000000 + (IXP425_EXP_CS_SIZE * \n)), \sz, \c, \b, \x, \p
81 .macro IXP_MAP_IO addr, sz
82 XSCALE_MMU_SECTION \addr>>20, \addr>>20, \sz>>20, 0, 0, 3, 0, 0
86 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
87 #define PLATFORM_SETUP1 _platform_setup1
88 #define CYGHWR_HAL_ARM_HAS_MMU
90 // ------------------------------------------------------------------------
91 // Define macro used to diddle the LEDs during early initialization.
92 // Can use r0+r1. Argument in \x.
93 #define CYGHWR_LED_MACRO DISPLAY \x, r0, r1
96 .macro DELAY cycles, reg0
104 // ------------------------------------------------------------------------
105 // This macro represents the initial startup code for the platform
106 .macro _platform_setup1
108 #ifdef CYGHWR_HAL_ARM_BIGENDIAN
110 mrc p15, 0, r0, c1, c0, 0
112 mcr p15, 0, r0, c1, c0, 0
116 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
119 // invalidate I & D caches & BTB
120 mcr p15, 0, r0, c7, c7, 0
123 // invalidate I & Data TLB
124 mcr p15, 0, r0, c8, c7, 0
127 // drain write and fill buffers
128 mcr p15, 0, r0, c7, c10, 4
131 // disable write buffer coalescing
132 mrc p15, 0, r0, c1, c0, 1
134 mcr p15, 0, r0, c1, c0, 1
137 // Setup chip selects
138 ldr r1, =IXP425_EXP_CFG_BASE
139 #ifdef IXP425_EXP_CS0_INIT
140 ldr r0, =IXP425_EXP_CS0_INIT
141 str r0, [r1, #IXP425_EXP_CS0]
143 #ifdef IXP425_EXP_CS1_INIT
144 ldr r0, =IXP425_EXP_CS1_INIT
145 str r0, [r1, #IXP425_EXP_CS1]
147 #ifdef IXP425_EXP_CS2_INIT
148 ldr r0, =IXP425_EXP_CS2_INIT
149 str r0, [r1, #IXP425_EXP_CS2]
151 #ifdef IXP425_EXP_CS3_INIT
152 ldr r0, =IXP425_EXP_CS3_INIT
153 str r0, [r1, #IXP425_EXP_CS3]
155 #ifdef IXP425_EXP_CS4_INIT
156 ldr r0, =IXP425_EXP_CS4_INIT
157 str r0, [r1, #IXP425_EXP_CS4]
159 #ifdef IXP425_EXP_CS5_INIT
160 ldr r0, =IXP425_EXP_CS5_INIT
161 str r0, [r1, #IXP425_EXP_CS5]
163 #ifdef IXP425_EXP_CS6_INIT
164 ldr r0, =IXP425_EXP_CS6_INIT
165 str r0, [r1, #IXP425_EXP_CS6]
167 #ifdef IXP425_EXP_CS7_INIT
168 ldr r0, =IXP425_EXP_CS7_INIT
169 str r0, [r1, #IXP425_EXP_CS7]
172 DISPLAY 0x1001, r7, r8
175 mrc p15, 0, r0, c1, c0, 0
176 orr r0, r0, #MMU_Control_I
177 mcr p15, 0, r0, c1, c0, 0
180 DISPLAY 0x1002, r7, r8
182 // Setup SDRAM controller
184 ldr r0, =IXP425_SDRAM_CFG_BASE
186 ldr r1, =IXP425_SDRAM_CONFIG_INIT
187 str r1, [r0, #IXP425_SDRAM_CONFIG]
189 // disable refresh cycles
191 str r1, [r0, #IXP425_SDRAM_REFRESH]
194 mov r1, #SDRAM_IR_NOP
195 str r1, [r0, #IXP425_SDRAM_IR]
198 // set SDRAM internal refresh val
199 ldr r1, =IXP425_SDRAM_REFRESH_CNT
200 str r1, [r0, #IXP425_SDRAM_REFRESH]
203 // send precharge-all command to close all open banks
204 mov r1, #SDRAM_IR_PRECHARGE
205 str r1, [r0, #IXP425_SDRAM_IR]
208 // provide 8 auto-refresh cycles
209 mov r1, #SDRAM_IR_AUTO_REFRESH
212 str r1, [r0, #IXP425_SDRAM_IR]
217 // set mode register in sdram
218 mov r1, #IXP425_SDRAM_SET_MODE_CMD
219 str r1, [r0, #IXP425_SDRAM_IR]
222 // start normal operation
223 mov r1, #SDRAM_IR_NORMAL
224 str r1, [r0, #IXP425_SDRAM_IR]
227 DISPLAY 0x1003, r7, r8
229 // Enable byte swapping control via page table P bit.
230 ldr r2, =IXP425_EXP_CFG_BASE
231 ldr r1, [r2, #IXP425_EXP_CNFG1]
232 orr r1, r1, #EXP_CNFG1_BYTE_SWAP_EN
233 str r1, [r2, #IXP425_EXP_CNFG1]
235 // value to load into pc to jump to real runtime address
237 #if defined(CYG_HAL_STARTUP_ROMRAM)
238 // R0 holds a RAM address for ROMRAM startup,
239 // so convert to a flash address.
240 orr r0, r0, #IXDP_FLASH_BASE
243 // Setup EXP_CNFG0 value to switch EXP bus out of low memory
244 ldr r2, =IXP425_EXP_CFG_BASE
245 ldr r1, [r2, #IXP425_EXP_CNFG0]
246 bic r1, r1, #EXP_CNFG0_MEM_MAP
248 ldr r4, =IXDP425_LED_DATA
254 // Here is where we switch from boot address (0x000000000) to the
255 // actual flash runtime address. We align to cache boundary so we
256 // execute from cache during the switchover. Cachelines are 8 words.
257 str r1, [r2, #IXP425_EXP_CNFG0] // make the EXP bus switch
263 strh r3, [r4] // We should never reach this point. If we do,
264 // display FFFF and loop forever.
268 DISPLAY 0x1004, r7, r8
270 #if defined(CYG_HAL_STARTUP_ROMRAM)
271 mov r0, #IXDP_FLASH_BASE
272 mov r1, #SDRAM_PHYS_BASE
273 ldr r2, =__ram_data_end
279 // start executing from RAM
285 // Build mmu tables into RAM so page table walks by the cpu
286 // don't interfere with FLASH programming.
287 mov r1, #SDRAM_PHYS_BASE
288 orr r1, r1, #0x4000 // RAM tables
289 add r2, r1, #0x4000 // End of tables
298 // Build section mappings
299 IXP_MAP_SDRAM SDRAM_BASE, 1, 0, 0, 0 // Cached SDRAM
300 IXP_MAP_SDRAM SDRAM_ALIAS_BASE, 1, 0, 0, 0 // Cached SDRAM alias
301 IXP_MAP_SDRAM SDRAM_UNCACHED_BASE, 0, 0, 0, 0 // Uncached SDRAM
302 IXP_MAP_SDRAM SDRAM_DC_BASE, 1, 0, 0, 1 // Cached data coherent SDRAM
304 IXP_MAP_EXP 0, IXDP_FLASH_SIZE, 1, 0, 0, 0 // Flash
305 IXP_MAP_EXP 2, IXDP425_LED_SIZE, 0, 0, 0, 0 // LED
306 IXP_MAP_EXP 4, (1 << 20), 0, 0, 0, 0 // NPE use
307 IXP_MAP_EXP 5, (1 << 20), 0, 0, 0, 0 // NPE use
309 IXP_MAP_EXP_V 0, IXDP_FLASH_DC_BASE, IXDP_FLASH_SIZE, 1, 0, 0, 1 // data coherent flash
311 IXP_MAP_IO IXP425_PCI_WINDOW_BASE, IXP425_PCI_WINDOW_SIZE
312 IXP_MAP_IO IXP425_QMGR_BASE, IXP425_QMGR_SIZE
313 IXP_MAP_IO IXP425_PCI_CFG_BASE, IXP425_PCI_CFG_SIZE
314 IXP_MAP_IO IXP425_EXP_CFG_BASE, IXP425_EXP_CFG_SIZE
315 IXP_MAP_IO IXP425_MISC_CFG_BASE, IXP425_MISC_CFG_SIZE
316 IXP_MAP_IO IXP425_SDRAM_CFG_BASE, IXP425_SDRAM_CFG_SIZE
318 DISPLAY 0x1005, r7, r8
320 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
323 // Set the TTB register to DRAM mmu_table
324 ldr r0, =(SDRAM_PHYS_BASE | 0x4000) // RAM tables
325 mcr p15, 0, r0, c2, c0, 0 // load page table pointer
328 // enable permission checks in all domains
330 mcr p15, 0, r0, c3, c0, 0
333 DISPLAY 0x1006, r7, r8
336 mrc p15, 0, r0, c1, c0, 0
337 orr r0, r0, #MMU_Control_M
338 orr r0, r0, #MMU_Control_R
339 mcr p15, 0, r0, c1, c0, 0
342 DISPLAY 0x1007, r7, r8
345 mrc p15, 0, r0, c1, c0, 0
346 orr r0, r0, #MMU_Control_C
347 mcr p15, 0, r0, c1, c0, 0
350 DISPLAY 0x1008, r7, r8
352 // Enable branch target buffer
353 mrc p15, 0, r0, c1, c0, 0
354 orr r0, r0, #MMU_Control_BTB
355 mcr p15, 0, r0, c1, c0, 0
358 DISPLAY 0x1009, r7, r8
360 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
363 mcr p15, 0, r0, c7, c7, 0 // flush Icache, Dcache and BTB
366 mcr p15, 0, r0, c8, c7, 0 // flush instuction and data TLBs
369 mcr p15, 0, r0, c7, c10, 4 // drain the write & fill buffers
372 DISPLAY 0x100A, r7, r8
375 ldr r1, =hal_dram_size /* [see hal_intr.h] */
379 DISPLAY 0x100B, r7, r8
381 .endm // _platform_setup1
383 #else // defined(CYG_HAL_STARTUP_ROM)
384 #define PLATFORM_SETUP1
387 #define PLATFORM_VECTORS _platform_vectors
388 .macro _platform_vectors
391 /*---------------------------------------------------------------------------*/
392 /* end of hal_platform_setup.h */
393 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */