1 #ifndef CYGONCE_HAL_PLATFORM_SETUP_H
2 #define CYGONCE_HAL_PLATFORM_SETUP_H
4 /*=============================================================================
6 // hal_platform_setup.h
8 // Platform specific support for HAL (assembly code)
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // Copyright (C) 2003 Gary Thomas <gary@mind.be>
17 // eCos is free software; you can redistribute it and/or modify it under
18 // the terms of the GNU General Public License as published by the Free
19 // Software Foundation; either version 2 or (at your option) any later version.
21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
23 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
26 // You should have received a copy of the GNU General Public License along
27 // with eCos; if not, write to the Free Software Foundation, Inc.,
28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
30 // As a special exception, if other files instantiate templates or use macros
31 // or inline functions from this file, or you compile this file and link it
32 // with other works to produce a work based on this file, this file does not
33 // by itself cause the resulting work to be covered by the GNU General Public
34 // License. However the source code for this file must still be made available
35 // in accordance with section (3) of the GNU General Public License.
37 // This exception does not invalidate any other reasons why a work based on
38 // this file might be covered by the GNU General Public License.
40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
41 // at http://sources.redhat.com/ecos/ecos-license/
42 // -------------------------------------------
43 //####ECOSGPLCOPYRIGHTEND####
44 //===========================================================================*/
46 #include <pkgconf/system.h> // System-wide configuration info
47 #include CYGBLD_HAL_VARIANT_H // Variant specific configuration
48 #include CYGBLD_HAL_PLATFORM_H // Platform specific configuration
49 #include <cyg/hal/hal_pxa2x0.h> // Variant specific hardware definitions
50 #include <cyg/hal/hal_mmu.h> // MMU definitions
51 #include <cyg/hal/hal_mm.h> // more MMU definitions
52 #include <cyg/hal/uE250.h> // Platform specific hardware definitions
53 #include <cyg/hal/hal_spd.h>
55 #define MDCNFG_VALUE 0x03001BC9
56 // #define MDCNFG_VALUE 0x00001BC9
57 #define MDMRS_VALUE 0x00000000
58 #define MDREFR_VALUE_1 0x00494030
59 #define MDREFR_VALUE_2 0x00094030
60 #define MDREFR_VALUE_3 0x0009C030
62 #define GPCR0_VALUE 0xFFFFFFFF
63 #define GPCR1_VALUE 0xFFFFFFFF
64 #define GPCR2_VALUE 0xFFFFFFFF
66 #define GPSR0_VALUE 0x00028000
67 #define GPSR1_VALUE 0x00002122
68 #define GPSR2_VALUE 0x0001C000
70 #define GPDR0_VALUE 0x03E3A080
71 #define GPDR1_VALUE 0x00FFA963
72 #define GPDR2_VALUE 0x0001C000
74 #define GAFR0_L_VALUE 0x88000000
75 #define GAFR0_U_VALUE 0x001A8010
76 #define GAFR1_L_VALUE 0x90900008
77 #define GAFR1_U_VALUE 0x0005AAAA
78 #define GAFR2_L_VALUE 0xA0000000
79 #define GAFR2_U_VALUE 0x00000002
81 #define PSSR_VALUE 0x20
82 #define MSC0_VALUE_NONBURST 0x2FD0
83 #define MSC0_VALUE_BURST 0x22D2
85 #if defined(CYG_HAL_STARTUP_ROM) || defined(CYG_HAL_STARTUP_ROMRAM)
86 #define PLATFORM_SETUP1 _platform_setup1
87 // #define PLATFORM_EXTRAS <cyg/hal/hal_platform_extras.h>
88 #define CYGHWR_HAL_ARM_HAS_MMU
90 // This macro represents the initial startup code for the platform
91 .macro _platform_setup1
92 // This is where we wind up immediately after reset. At this point, we
93 // are executing from the boot address (0x00000000), not the eventual
94 // flash address. Do some basic setup using position independent code
95 // then switch to real flash address
97 // FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME
98 // This is a quick and dirty workaround to an apparent gas/ld
99 // bug. The computed UNMAPPED_PTR(reset_vector) is off by 0x20.
103 // FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME FIXME
106 // Set the direction of the LED GPIO's to 'output'
107 // This will disable the LED's (which are on at boot-time, so we
108 // can see we have safely landed here.
109 ldr r1, =PXA2X0_GPDR0
114 // Disable interrupts, by setting the Interrupt Mask Registers to all 0's
121 mcr p15, 0, r0, c1, c0, 0
125 mcr p15, 0, r0, c8, c7, 0 // Flush TLB
127 // flush I&D caches and BTB
129 mcr p15, 0, r0, c7, c7, 0 // Flush caches
133 // Enables access to coprocessor 0 (The only extra coprocessor on the PXA250)
135 mcr p15, 0, r0, c15, c1, 0
137 // Disable the IRQ's and FIQ's in the program status register and
138 // enable supervisor mode
139 ldr r0,=(CPSR_IRQ_DISABLE|CPSR_FIQ_DISABLE|CPSR_SUPERVISOR_MODE)
149 mcr p14, 0, r1, c6, c0, 0
151 // Set-up memory according to NMI specs
153 ldr r1,=PXA2X0_RAM_BANK0_BASE
163 // Set DRAM Configuration Value
164 ldr r1,=PXA2X0_MDCNFG
173 // Set Refresh Values
174 ldr r1,=PXA2X0_MDREFR
175 ldr r2,=MDREFR_VALUE_1
178 ldr r1,=PXA2X0_MDREFR
179 ldr r2,=MDREFR_VALUE_2
182 ldr r1,=PXA2X0_MDREFR
183 ldr r2,=MDREFR_VALUE_3
186 // Set Static memory registers
188 ldr r2,=MSC0_VALUE_NONBURST
191 // Setup GPIO clear registers
192 ldr r1, =PXA2X0_GPCR0
193 ldr r2, =(GPCR0_VALUE)
196 ldr r1, =PXA2X0_GPCR1
197 ldr r2, =(GPCR1_VALUE)
200 ldr r1, =PXA2X0_GPCR2
201 ldr r2, =(GPCR2_VALUE)
204 // Setup GPIO set registers
205 ldr r1, =PXA2X0_GPSR0
206 ldr r2, =(GPSR0_VALUE)
209 ldr r1, =PXA2X0_GPSR1
210 ldr r2, =(GPSR1_VALUE)
213 ldr r1, =PXA2X0_GPSR2
214 ldr r2, =(GPSR2_VALUE)
217 // Setup GPIO direction registers
218 ldr r1, =PXA2X0_GPDR0
219 ldr r2, =(GPDR0_VALUE)
222 ldr r1, =PXA2X0_GPDR1
223 ldr r2, =(GPDR1_VALUE)
226 ldr r1, =PXA2X0_GPDR2
227 ldr r2, =(GPDR2_VALUE)
230 // Setup GPIO alternate function registers
231 ldr r1, =PXA2X0_GAFR0_L
232 ldr r2, =(GAFR0_L_VALUE)
235 ldr r1, =PXA2X0_GAFR0_U
236 ldr r2, =(GAFR0_U_VALUE)
239 ldr r1, =PXA2X0_GAFR1_L
240 ldr r2, =(GAFR1_L_VALUE)
243 ldr r1, =PXA2X0_GAFR1_U
244 ldr r2, =(GAFR1_U_VALUE)
247 ldr r1, =PXA2X0_GAFR2_L
248 ldr r2, =(GAFR2_L_VALUE)
251 ldr r1, =PXA2X0_GAFR2_U
252 ldr r2, =(GAFR2_U_VALUE)
256 ldr r2, =(PSSR_VALUE)
260 mrc p15, 0, r0, c1, c0, 0
261 orr r0, r0, #MMU_Control_I
262 mcr p15, 0, r0, c1, c0, 0
270 // Set up a stack [for calling C code]
271 ldr r1,=__startup_stack
272 ldr r2,=PXA2X0_RAM_BANK0_BASE
285 ldr r1,=MMU_Control_Init|MMU_Control_M
286 mcr MMU_CP,0,r1,MMU_Control,c0
300 #else // defined(CYG_HAL_STARTUP_ROM)
301 #define PLATFORM_SETUP1
304 #define PLATFORM_VECTORS _platform_vectors
305 .macro _platform_vectors
306 .globl hal_pcsr_cfg_retry
307 hal_pcsr_cfg_retry: .long 0 // Boot-time value of PCSR Retry bit.
310 /*---------------------------------------------------------------------------*/
311 /* end of hal_platform_setup.h */
312 #endif /* CYGONCE_HAL_PLATFORM_SETUP_H */