1 //==========================================================================
5 // FPGA support for NMI uEngine uE250 PCI
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 2003 Gary Thomas <gary@mind.be>
13 // eCos is free software; you can redistribute it and/or modify it under
14 // the terms of the GNU General Public License as published by the Free
15 // Software Foundation; either version 2 or (at your option) any later version.
17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 // You should have received a copy of the GNU General Public License along
23 // with eCos; if not, write to the Free Software Foundation, Inc.,
24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 // As a special exception, if other files instantiate templates or use macros
27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
29 // by itself cause the resulting work to be covered by the GNU General Public
30 // License. However the source code for this file must still be made available
31 // in accordance with section (3) of the GNU General Public License.
33 // This exception does not invalidate any other reasons why a work based on
34 // this file might be covered by the GNU General Public License.
36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 // at http://sources.redhat.com/ecos/ecos-license/
38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): David Mazur <david@mind.be>
44 // Contributors: gthomas
46 // Purpose: FPGA support
49 //####DESCRIPTIONEND####
51 //========================================================================*/
53 #include <pkgconf/hal.h>
54 #include <pkgconf/system.h>
55 #include CYGBLD_HAL_PLATFORM_H
56 #include CYGHWR_MEMORY_LAYOUT_H
58 #include <cyg/infra/cyg_type.h> // base types
59 #include <cyg/infra/cyg_trac.h> // tracing macros
60 #include <cyg/infra/cyg_ass.h> // assertion macros
61 #include <cyg/infra/diag.h> // diagnostic printing
63 #include <cyg/hal/hal_io.h> // IO macros
64 #include <cyg/hal/hal_if.h> // calling interface API
65 #include <cyg/hal/hal_arch.h> // Register state info
66 #include <cyg/hal/hal_diag.h>
67 #include <cyg/hal/hal_intr.h> // Interrupt names
68 #include <cyg/hal/hal_cache.h>
69 #include <cyg/io/pci_hw.h>
70 #include <cyg/io/pci.h>
72 #include <cyg/hal/plx.h>
74 #define FPGA_PROG 0x00020000
75 #define FPGA_INIT 0x00000002
76 #define FPGA_DONE 0x00080000
78 #define _FPGA_PROG_BASE 0x0c000000
79 #define FPGA_PROG_BASE (*((volatile cyg_uint32 *)(_FPGA_PROG_BASE)))
81 #define FPGA_DONE_DRV 0x8
82 #define FPGA_INIT_DRV 0x10
83 #define FPGA_WRITE 0x20
85 #define VGA_PROG_CTRL 0x4008
86 #define VGA_PROG_DATA 0x400C
91 #define VGA_DONE_DRV 0x8
92 #define VGA_INIT_DRV 0x10
93 #define VGA_WRITE 0x20
96 #include <cyg/compress/zlib.h>
100 static z_stream stream;
102 #define FEEDBACK_COUNT 16
103 #define ZCHAR_BUF_SIZE 256
105 char buf[ZCHAR_BUF_SIZE];
112 // Internal allocator for decompression - just use bottom of heap
113 // which will be reclaimed by eCos once the system is initialized
115 _zcalloc(void *opaque, unsigned int items, unsigned int size)
117 static char *ptr = (char *)&_end;
120 // diag_printf("%s(%p,%d,%d) = %p\n", __FUNCTION__, opaque, items, size, res);
126 _zcfree(void *opaque, void *ptr)
128 // diag_printf("%s(%p,%p)\n", __FUNCTION__, opaque, ptr);
135 struct _zchar_info *info = (struct _zchar_info *)stream.opaque;
136 static char spin[] = "|/-\\|-";
139 if (info->avail == 0) {
140 stream.next_out = info->buf;
141 stream.avail_out = sizeof(info->buf);
142 info->ptr = info->buf;
143 err = inflate(&stream, Z_SYNC_FLUSH);
144 info->avail = (char *)stream.next_out - info->buf;
145 if (--info->feedback == 0) {
146 diag_printf("%c\b", spin[tick++]);
147 if (tick >= (sizeof(spin)-1)) {
150 info->feedback = FEEDBACK_COUNT;
156 return *(info->ptr)++;
158 // End of data stream
164 * A little bit swapping function, necessary due to the xilinx bit file format.
166 static const cyg_uint8 _swapped[] = {
167 0x00, 0x08, 0x04, 0x0C, 0x02, 0x0A, 0x06, 0x0E,
168 0x01, 0x09, 0x05, 0x0D, 0x03, 0x0B, 0x07, 0x0F
172 bitswap(cyg_uint8 byte)
174 cyg_uint8 _new = (_swapped[byte & 0x0F] << 4) | (_swapped[(byte >> 4) & 0x0F]);
178 typedef int _bitfile_fun(void);
179 typedef void _download_fun(_bitfile_fun *_bitfile);
182 * Gets the tag at given location in the bitfile.
185 bitfile_get_tag(_bitfile_fun *_bitfile)
187 return (*_bitfile)();
191 bitfile_get_len16(_bitfile_fun *_bitfile)
195 length = (*_bitfile)() << 8;
196 length |= (*_bitfile)();
202 bitfile_get_len32(_bitfile_fun *_bitfile)
206 length = (*_bitfile)() << 24;
207 length |= (*_bitfile)() << 16;
208 length |= (*_bitfile)() << 8;
209 length |= (*_bitfile)();
215 * Process a string tag.
218 bitfile_process_string_tag(char *description, _bitfile_fun *_bitfile)
222 len = bitfile_get_len16(_bitfile);
223 diag_printf(description);
224 for (i = 0; i < len; i++) {
225 diag_printf("%c", (*_bitfile)());
230 * Process the 'e' tag in the bit file, which is the actual code that is to
231 * be programmed on the fpga.
234 bitfile_process_tag_e(_bitfile_fun *_bitfile)
240 len = bitfile_get_len32(_bitfile);
242 *PXA2X0_GPCR0 = FPGA_PROG;
244 for (count=0; count<10000; count++)
245 if ((*PXA2X0_GPLR0 & FPGA_INIT) == 0)
247 if ((*PXA2X0_GPLR0 & FPGA_INIT) != 0)
248 diag_printf("INIT did not go low. FPGA programming failed\n");
250 *PXA2X0_GPSR0 = FPGA_PROG;
252 for (count=0; count<10000; count++)
253 if ((*PXA2X0_GPLR0 & FPGA_INIT) != 0)
255 if ((*PXA2X0_GPLR0 & FPGA_INIT) == 0)
256 diag_printf("INIT did not go high. FPGA programming failed\n");
258 for( i=0; i<len; i++) {
259 if ((*PXA2X0_GPLR0 & FPGA_INIT) == 0) {
260 diag_printf("CRC Error. FPGA programming failed\n");
263 byte = (*_bitfile)();
266 if (byte & (0x01 << 7)) word|=(0x01);
267 if (byte & (0x01 << 6)) word|=(0x01 << 18);
268 if (byte & (0x01 << 5)) word|=(0x01 << 14);
269 if (byte & (0x01 << 4)) word|=(0x01 << 1);
270 if (byte & (0x01 << 3)) word|=(0x01 << 4);
271 if (byte & (0x01 << 2)) word|=(0x01 << 6);
272 if (byte & (0x01 << 1)) word|=(0x01 << 9);
273 if (byte & (0x01)) word|=(0x01 << 30);
275 FPGA_PROG_BASE = word;
278 for (count=0; count<10000; count++)
279 if ((*PXA2X0_GPLR0 & FPGA_DONE) != 0)
281 if ((*PXA2X0_GPLR0 & FPGA_DONE) == 0)
282 diag_printf("DONE did not go high. FPGA programming failed\n");
287 * Process the 'e' tag in the bit file, which is the actual code that is to
288 * be programmed on the fpga.
291 vga_bitfile_process_tag_e(_bitfile_fun *_bitfile)
296 len = bitfile_get_len32(_bitfile);
298 localbus_writeb(VGA_WRITE, VGA_PROG_CTRL);
299 localbus_writeb(VGA_WRITE | VGA_PROG, VGA_PROG_CTRL);
301 for (count=0; count<10000; count++)
302 if (localbus_readb(VGA_PROG_CTRL) & VGA_INIT)
304 if (!(localbus_readb(VGA_PROG_CTRL) & VGA_INIT))
305 diag_printf("INIT did not go high. VGA FPGA programming failed\n");
307 localbus_writeb(VGA_PROG, VGA_PROG_CTRL);
309 for (i=0; i<len; i++) {
310 byte = (*_bitfile)();
311 localbus_writeb(bitswap(byte),VGA_PROG_DATA);
314 for (count=0; count<10000; count++)
315 if (localbus_readb(VGA_PROG_CTRL) & VGA_DONE)
317 if (!(localbus_readb(VGA_PROG_CTRL) & VGA_DONE))
318 diag_printf("DONE did not go high. VGA FPGA programming failed\n");
320 localbus_writeb(VGA_PROG | VGA_WRITE, VGA_PROG_CTRL);
324 // Download a bitstream
327 download_bitstream(char *title, _bitfile_fun *_bitfile, _download_fun *_download)
331 diag_printf("Load %s(", title);
333 len = bitfile_get_len16(_bitfile);
335 (*_bitfile)(); // Skip
337 len = bitfile_get_len16(_bitfile);
342 tag = bitfile_get_tag(_bitfile);
345 bitfile_process_string_tag("Design:", _bitfile);
349 bitfile_process_string_tag(", Part:", _bitfile);
353 bitfile_process_string_tag(", Date:", _bitfile);
357 bitfile_process_string_tag(" ", _bitfile);
361 (*_download)(_bitfile);
365 diag_printf("Unknown tag. aborting...\n");
373 * Process a bitfile located at the given address.
376 load_fpga(cyg_uint8 *compressed_bitfile, int len)
379 struct _zchar_info zchar_data;
381 stream.zalloc = _zcalloc;
382 stream.zfree = _zcfree;
383 stream.next_in = compressed_bitfile;
384 stream.avail_in = len;
386 stream.avail_out = 0;
387 stream.opaque = (void *)&zchar_data;
388 zchar_data.avail = 0;
389 zchar_data.feedback = FEEDBACK_COUNT;
390 zchar_data.total = 0;
391 err = inflateInit(&stream);
393 diag_printf("%s: Can't init stream\n", __FUNCTION__);
396 // Set up to download FPGA bitstreap
397 *PXA2X0_GPSR0 = FPGA_PROG;
398 download_bitstream("PCI ctlr", _zchar, bitfile_process_tag_e);
400 diag_printf(") %x bytes\n", zchar_data.total);
404 * Process a bitfile located at the given address.
407 load_vga(cyg_uint8 *compressed_bitfile, int len)
410 struct _zchar_info zchar_data;
412 stream.zalloc = _zcalloc;
413 stream.zfree = _zcfree;
414 stream.next_in = compressed_bitfile;
415 stream.avail_in = len;
417 stream.avail_out = 0;
418 stream.opaque = (void *)&zchar_data;
419 zchar_data.avail = 0;
420 zchar_data.feedback = FEEDBACK_COUNT;
421 zchar_data.total = 0;
422 err = inflateInit(&stream);
424 diag_printf("%s: Can't init stream\n", __FUNCTION__);
427 download_bitstream("VGA ctlr", _zchar, vga_bitfile_process_tag_e);
429 diag_printf(") %x bytes\n", zchar_data.total);