1 //=============================================================================
5 // Miscellaneous platform support for xsengine
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2005 eCosCentric Ltd.
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20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
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31 // License. However the source code for this file must still be made available
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37 // -------------------------------------------
38 //####ECOSGPLCOPYRIGHTEND####
39 //=============================================================================
40 //#####DESCRIPTIONBEGIN####
42 // Author(s): Knud Woehler <knud.woehler@microplex.de>
45 //####DESCRIPTIONEND####
47 #include <pkgconf/hal.h>
48 #include <pkgconf/system.h>
49 #include CYGBLD_HAL_PLATFORM_H
51 #include <cyg/infra/cyg_type.h> // base types
52 #include <cyg/infra/cyg_trac.h> // tracing macros
53 #include <cyg/infra/cyg_ass.h> // assertion macros
54 #include <cyg/hal/hal_io.h> // IO macros
55 #include <cyg/hal/hal_arch.h> // Register state info
56 #include <cyg/hal/hal_diag.h>
57 #include <cyg/hal/hal_intr.h> // Interrupt names
58 #include <cyg/hal/hal_cache.h>
59 #include <cyg/hal/hal_pxa2x0.h>
60 #include <cyg/hal/xsengine.h> // Platform specifics
61 #include <cyg/infra/diag.h> // diag_printf
62 #include <cyg/hal/hal_mm.h>
64 #include <string.h> // memset
69 // Set up the translation tables at offset 0x4000
70 unsigned long ttb_base = PXA2X0_RAM_BANK0_BASE + 0x4000;
73 // Set the TTB register
74 asm volatile ("mcr p15,0,%0,c2,c0,0" : : "r"(ttb_base) /*:*/);
76 // Set the Domain Access Control Register
77 i = ARM_ACCESS_DACR_DEFAULT;
78 asm volatile ("mcr p15,0,%0,c3,c0,0" : : "r"(i) /*:*/);
80 // First clear all TT entries - ie Set them to Faulting
81 memset((void *)ttb_base, 0, ARM_FIRST_LEVEL_PAGE_TABLE_SIZE);
83 /* Actual Virtual Size Attributes Function */
84 /* Base Base MB cached? buffered? access permissions */
85 /* xxx00000 xxx00000 */
86 #define _CACHED ARM_CACHEABLE
87 #define _UNCACHED ARM_UNCACHEABLE
88 #define _BUF ARM_BUFFERABLE
89 #define _NOBUF ARM_UNBUFFERABLE
90 #define _RWRW ARM_ACCESS_PERM_RW_RW
91 X_ARM_MMU_SECTION(0x000, 0x500, 32, _UNCACHED, _NOBUF, _RWRW); /* Boot flash ROMspace */
92 X_ARM_MMU_SECTION(0x040, 0x600, 32, _UNCACHED, _NOBUF, _RWRW); /* LAN chip */
93 X_ARM_MMU_SECTION(0x0C0, 0x700, 32, _UNCACHED, _NOBUF, _RWRW); /* FPGA chip */
94 X_ARM_MMU_SECTION(0xA00, 0x000, 64, _CACHED, _BUF, _RWRW); /* SDRAM Bank 0 */
95 X_ARM_MMU_SECTION(0xA00, 0xC00, 64, _UNCACHED, _BUF, _RWRW); /* SDRAM Bank 0 */
96 X_ARM_MMU_SECTION(0xE00, 0xE00, 128, _CACHED, _BUF, _RWRW); /* Zeros (Cache Clean) Bank */
97 X_ARM_MMU_SECTION(0x400, 0x400, 64, _UNCACHED, _NOBUF, _RWRW); /* Peripheral Registers */
98 X_ARM_MMU_SECTION(0x440, 0x440, 64, _UNCACHED, _NOBUF, _RWRW); /* LCD Registers */
99 X_ARM_MMU_SECTION(0x480, 0x480, 64, _UNCACHED, _NOBUF, _RWRW); /* Memory Ctl Registers */
103 // Platform specific initialization
107 plf_hardware_init(void)
109 // RAM startup only - rewrite relevent bits depending on config
110 #ifndef CYG_HAL_STARTUP_ROM
111 HAL_DCACHE_SYNC(); // Force data out
112 HAL_DCACHE_INVALIDATE_ALL(); // Flush TLBs: make new mmu state effective
113 #endif // ! CYG_HAL_STARTUP_ROM - RAM start only
118 // ------------------------------------------------------------------------
119 // EOF xsengine_misc.c