1 #ifndef CYGONCE_HAL_CALM32_REGS_H
2 #define CYGONCE_HAL_CALM32_REGS_H
3 //========================================================================
7 // Register defines for CalmRISC 16 processors
9 //========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 //========================================================================
43 //#####DESCRIPTIONBEGIN####
45 // Author(s): Red Hat, msalter
46 // Contributors: Red Hat, msalter
49 // Description: Register defines for CalmRISC 16 processors
52 //####DESCRIPTIONEND####
54 //========================================================================
56 #include <pkgconf/hal.h>
58 #ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
60 // This value must agree with NUMREGS in calm32-stub.h.
66 // Status register fields
67 #define SR_T 0x00000001 // TRUE flag
68 #define SR_V 0x00000008 // Overflow flag
69 #define SR_Z0 0x00000010 // R6 Zero flag
70 #define SR_Z1 0x00000020 // R7 Zero flag.
71 #define SR_DS 0x00000040 // Divisor sign
72 #define SR_QT 0x00000080 // Quotient
73 #define SR_BX 0x00001000 // Byte sign extension
74 #define SR_HX 0x00002000 // Halfword sign extension
75 #define SR_SYSX_MASK 0x000f0000 // system extension
76 #define SR_SYSX_SHIFT 16
77 #define SR_IE 0x01000000 // IRQ enable
78 #define SR_FE 0x02000000 // FIQ enable
79 #define SR_TE 0x04000000 // Trace enable
80 #define SR_BS 0x10000000 // FIQ enable
81 #define SR_RS0 0x20000000 // Register bank select
82 #define SR_RS1 0x40000000 // Register bank select
83 #define SR_PM 0x80000000 // Privilege mode
85 #endif // ifdef CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
87 #endif // ifndef CYGONCE_HAL_CALM32_REGS_H