1 //========================================================================
5 // Helper functions for stub, generic to all CalmRISC32 processors
7 //========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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19 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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27 // or inline functions from this file, or you compile this file and link it
28 // with other works to produce a work based on this file, this file does not
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Red Hat, msalter
44 // Contributors: Red Hat, msalter
47 // Description: Helper functions for stub, generic to CalmRISC32 processors
50 //####DESCRIPTIONEND####
52 //========================================================================
56 #include <pkgconf/hal.h>
59 #include <pkgconf/redboot.h>
62 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
64 #include <cyg/hal/hal_stub.h>
66 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
68 #include <cyg/hal/hal_arch.h>
69 #include <cyg/hal/hal_intr.h>
71 typedef cyg_uint16 t_inst;
73 /*----------------------------------------------------------------------
74 * Asynchronous interrupt support
83 /* Called to asynchronously interrupt a running program.
84 Must be passed address of instruction interrupted.
85 This is typically called in response to a debug port
90 install_async_breakpoint(void *pc)
92 asyncBuffer.targetAddr = pc;
93 asyncBuffer.savedInstr = *(t_inst *)pc;
94 *(t_inst *)pc = *(t_inst *)_breakinst;
95 __instruction_cache(CACHE_FLUSH);
96 __data_cache(CACHE_FLUSH);
99 /*--------------------------------------------------------------------*/
100 /* Given a trap value TRAP, return the corresponding signal. */
102 int __computeSignal (unsigned int trap_number)
104 switch (trap_number) {
105 case CYGNUM_HAL_VECTOR_FIQ:
106 case CYGNUM_HAL_VECTOR_IRQ:
108 case CYGNUM_HAL_VECTOR_IABRT:
109 case CYGNUM_HAL_VECTOR_DABRT:
115 /* Return the trap number corresponding to the last-taken trap. */
117 int __get_trap_number (void)
119 // The vector is not not part of the GDB register set so get it
120 // directly from the save context.
121 return _hal_registers->vector;
124 #if defined(CYGSEM_REDBOOT_BSP_SYSCALLS)
125 int __is_bsp_syscall(void)
127 return __get_trap_number() >= CYGNUM_HAL_VECTOR_SWI;
131 /* Set the current pc register value based on current vector. */
133 void set_pc (target_register_t pc)
135 put_register (REG_PC, pc);
136 switch (__get_trap_number()) {
137 case CYGNUM_HAL_VECTOR_SWI:
138 put_register (REG_SPC_SWI, pc);
140 case CYGNUM_HAL_VECTOR_FIQ:
141 put_register (REG_SPC_FIQ, pc);
143 case CYGNUM_HAL_VECTOR_IRQ:
144 put_register (REG_SPC_IRQ, pc);
147 put_register (REG_SPC_EXPT, pc);
152 /* Get the current pc register value based on current vector. */
154 target_register_t get_pc(void)
156 switch (__get_trap_number()) {
157 case CYGNUM_HAL_VECTOR_SWI:
158 return get_register (REG_SPC_SWI);
159 case CYGNUM_HAL_VECTOR_FIQ:
160 return get_register (REG_SPC_FIQ);
161 case CYGNUM_HAL_VECTOR_IRQ:
162 return get_register (REG_SPC_IRQ);
166 return get_register (REG_SPC_EXPT);
169 int __sp_regnum(void)
171 target_register_t sr = get_register(REG_SR);
173 if ((sr & CYGARC_SR_PM) == 0 || (sr & CYGARC_SR_BS) == 0)
178 /*----------------------------------------------------------------------
179 * Single-step support
182 /* Set things up so that the next user resume will execute one instruction.
183 This may be done by setting breakpoints or setting a single step flag
184 in the saved user registers, for example. */
186 void __single_step (void)
188 put_register(REG_SR, get_register(REG_SR) | CYGARC_SR_TE);
192 /* Clear the single-step state. */
194 void __clear_single_step (void)
196 put_register(REG_SR, get_register(REG_SR) & ~CYGARC_SR_TE);
200 void __install_breakpoints ()
202 /* Install the breakpoints in the breakpoint list */
203 __install_breakpoint_list();
206 void __clear_breakpoints (void)
208 __clear_breakpoint_list();
212 /* If the breakpoint we hit is in the breakpoint() instruction, return a
216 __is_breakpoint_function ()
218 return get_pc() == (target_register_t)(unsigned long)&_breakinst;
222 /* Skip the current instruction. Since this is only called by the
223 stub when the PC points to a breakpoint or trap instruction,
224 we can safely just skip 2. */
226 void __skipinst (void)
228 set_pc(get_pc() + 2);
231 int __is_prog_addr(unsigned long long addr)
233 return addr >= 0x100000000ULL;
236 char *__addr_to_ptr(unsigned long long addr)
238 return (char *)((unsigned)(addr & 0xffffffff));
241 unsigned short __read_prog_uint16(void *addr)
244 asm("ldch %0, @%1" : "=r"(val) : "r"(addr) );
248 unsigned char __read_prog_uint8(void *addr)
251 int is_odd = ((unsigned)addr & 1) == 1;
253 s = __read_prog_uint16((void *)((unsigned)addr & ~1));
257 return (s >> 8) & 0xff;
260 unsigned int __read_prog_uint32(void *addr)
264 u = __read_prog_uint16(addr) << 16;
265 u |= __read_prog_uint16((void *)((unsigned)addr + 2));
270 void __write_prog_uint16(void *addr, unsigned short val)
272 hal_plf_write_prog_halfword((unsigned)addr, val);
275 void __write_prog_uint32(void *addr, unsigned int val)
277 hal_plf_write_prog_halfword((unsigned)addr, (val >> 16) & 0xffff);
278 hal_plf_write_prog_halfword((unsigned)addr + 2, val & 0xffff);
281 void __write_prog_uint8(void *addr, unsigned char val)
284 int is_odd = ((unsigned)addr & 1) == 1;
286 s = __read_prog_uint16((void *)((unsigned)addr & ~1));
289 s = (s & 0xff00) | val;
291 s = (s & 0xff) | (val << 8);
293 hal_plf_write_prog_halfword((unsigned)addr & ~1, s);
297 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS