1 //==========================================================================
5 // HAL misc board support definitions for Fujitsu FR5xx chips
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas
46 // Purpose: Platform register definitions
49 //####DESCRIPTIONEND####
51 //========================================================================*/
53 #ifndef __HAL_FR500_H__
54 #define __HAL_FR500_H__ 1
58 #define _FRV550_SDRAM_CTL 0xFEFF0200 // Control
59 #define _FRV550_SDRAM_AMC 0xFEFF0204 // Access mode control
60 #define _FRV550_SDRAM_MS 0xFEFF0208 // Mode select
61 #define _FRV550_SDRAM_CFG 0xFEFF020C // Configuration
62 #define _FRV550_SDRAM_AN 0xFEFF0210 // Address number
63 #define _FRV550_SDRAM_STS 0xFEFF0214 // Status
64 #define _FRV550_SDRAM_RCN 0xFEFF0218 // Refresh control
65 #define _FRV550_SDRAM_ART 0xFEFF021C // Auto-refresh timer
67 #define _FRV550_SDRAM_ARS0 0xFEFF0100 // Address #0
68 #define _FRV550_SDRAM_ARS1 0xFEFF0104 // Address #1
69 #define _FRV550_SDRAM_ARS2 0xFEFF0108 // Address #2
70 #define _FRV550_SDRAM_ARS3 0xFEFF010C // Address #3
71 #define _FRV550_SDRAM_AMK0 0xFEFF0110 // Address mask #0
72 #define _FRV550_SDRAM_AMK1 0xFEFF0114 // Address mask #1
73 #define _FRV550_SDRAM_AMK2 0xFEFF0118 // Address mask #2
74 #define _FRV550_SDRAM_AMK3 0xFEFF011C // Address mask #3
77 #define _FRV550_LBUS_CP 0xFEFF1000 // Controller protect
78 #define _FRV550_LBUS_GCR 0xFEFF1010 // General configuration
79 #define _FRV550_LBUS_EST 0xFEFF1020 // Error status
80 #define _FRV550_LBUS_EAD 0xFEFF1028 // Error address
81 #define _FRV550_LBUS_MAICR 0xFEFF1030 // Master access interval control
82 #define _FRV550_LBUS_EMBR 0xFEFF1040 // External master base
83 #define _FRV550_LBUS_EMAM 0xFEFF1048 // External master address mask
84 #define _FRV550_LBUS_CR0 0xFEFF1100 // Configuration - space #0
85 #define _FRV550_LBUS_CR1 0xFEFF1108 // Configuration - space #1
86 #define _FRV550_LBUS_CR2 0xFEFF1110 // Configuration - space #2
87 #define _FRV550_LBUS_CR3 0xFEFF1118 // Configuration - space #3
88 #define _FRV550_LBUS_CR4 0xFEFF1120 // Configuration - space #4
89 #define _FRV550_LBUS_CR5 0xFEFF1128 // Configuration - space #5
90 #define _FRV550_LBUS_CR6 0xFEFF1130 // Configuration - space #6
91 #define _FRV550_LBUS_CR7 0xFEFF1138 // Configuration - space #7
92 #define _FRV550_LBUS_BR0 0xFEFF1C00 // Slave - base address #0
93 #define _FRV550_LBUS_BR1 0xFEFF1C08 // Slave - base address #1
94 #define _FRV550_LBUS_BR2 0xFEFF1C10 // Slave - base address #2
95 #define _FRV550_LBUS_BR3 0xFEFF1C18 // Slave - base address #3
96 #define _FRV550_LBUS_BR4 0xFEFF1C20 // Slave - base address #4
97 #define _FRV550_LBUS_BR5 0xFEFF1C28 // Slave - base address #5
98 #define _FRV550_LBUS_BR6 0xFEFF1C30 // Slave - base address #6
99 #define _FRV550_LBUS_BR7 0xFEFF1C38 // Slave - base address #7
100 #define _FRV550_LBUS_AM0 0xFEFF1D00 // Slave - address mask #0
101 #define _FRV550_LBUS_AM1 0xFEFF1D08 // Slave - address mask #1
102 #define _FRV550_LBUS_AM2 0xFEFF1D10 // Slave - address mask #2
103 #define _FRV550_LBUS_AM3 0xFEFF1D18 // Slave - address mask #3
104 #define _FRV550_LBUS_AM4 0xFEFF1D20 // Slave - address mask #4
105 #define _FRV550_LBUS_AM5 0xFEFF1D28 // Slave - address mask #5
106 #define _FRV550_LBUS_AM6 0xFEFF1D30 // Slave - address mask #6
107 #define _FRV550_LBUS_AM7 0xFEFF1D38 // Slave - address mask #7
110 #define _FRV550_HW_RESET 0xFEFFF500 // Hardware reset
113 #define _FRV550_GPIO_SIR 0xFEFFF410 // Special input signals
114 #define _FRV550_GPIO_SOR 0xFEFFF418 // Special output signals
116 #endif // __HAL_FR500_H__