packages/hal/frv/arch/v2_0/include/hal_cache.h

   1 #ifndef CYGONCE_HAL_CACHE_H
   2 #define CYGONCE_HAL_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      hal_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
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  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   gthomas
  47 // Contributors:hmt
  48 // Date:        2000-05-08
  49 // Purpose:     Cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations.
  52 // Usage:
  53 //              #include <cyg/hal/hal_cache.h>
  54 //              ...
  55 //
  56 //
  57 //####DESCRIPTIONEND####
  58 //
  59 //=============================================================================
  60
  61 #include <cyg/infra/cyg_type.h>
  62 #include CYGBLD_HAL_PLF_DEFS_H
  63 #include <cyg/hal/plf_cache.h>      // Platform (model) details
  64
  65 //-----------------------------------------------------------------------------
  66 // Global control of Instruction cache
  67
  68 // Enable the instruction cache
  69 #define HAL_ICACHE_ENABLE()                     \
  70 CYG_MACRO_START                                 \
  71     cyg_uint32 mask = _HSR0_ICE;                \
  72     asm volatile (                              \
  73         "movsg hsr0,gr4\n"                      \
  74         "\tor    gr4,%0,gr4\n"                  \
  75         "\tmovgs gr4,hsr0\n"                    \
  76         :                                       \
  77         : "r"(mask)                             \
  78         : "gr4" /* Clobber list */              \
  79         );                                      \
  80 CYG_MACRO_END
  81
  82 // Disable the instruction cache (and invalidate it, required semanitcs)
  83 #define HAL_ICACHE_DISABLE()                    \
  84 CYG_MACRO_START                                 \
  85     cyg_uint32 mask = ~_HSR0_ICE;               \
  86     asm volatile (                              \
  87         "movsg hsr0,gr4\n"                      \
  88         "\tand   gr4,%0,gr4\n"                  \
  89         "\tmovgs gr4,hsr0\n"                    \
  90         :                                       \
  91         : "r"(mask)                             \
  92         : "gr4" /* Clobber list */              \
  93         );                                      \
  94 CYG_MACRO_END
  95
  96 // Query the state of the instruction cache
  97 #define HAL_ICACHE_IS_ENABLED(_state_)          \
  98 CYG_MACRO_START                                 \
  99     register cyg_uint32 reg;                    \
 100     asm volatile ("movsg hsr0,%0"               \
 101                   : "=r"(reg)                   \
 102                   :                             \
 103         );                                      \
 104     (_state_) = (0 != (_HSR0_ICE & reg));       \
 105 CYG_MACRO_END
 106
 107 // Invalidate the entire cache
 108 #define HAL_ICACHE_INVALIDATE_ALL()             \
 109 CYG_MACRO_START                                 \
 110     asm volatile ("icei @(gr4,gr0),1"           \
 111                   :                             \
 112                   :                             \
 113         );                                      \
 114 CYG_MACRO_END
 115
 116 // Synchronize the contents of the cache with memory.
 117 // (which includes flushing out pending writes)
 118 #define HAL_ICACHE_SYNC()                                       \
 119 CYG_MACRO_START                                                 \
 120     HAL_DCACHE_SYNC(); /* ensure data gets to RAM */            \
 121     HAL_ICACHE_INVALIDATE_ALL(); /* forget all we know */       \
 122 CYG_MACRO_END
 123
 124 // Set the instruction cache refill burst size
 125 //#define HAL_ICACHE_BURST_SIZE(_size_)
 126
 127 // Load the contents of the given address range into the instruction cache
 128 // and then lock the cache so that it stays there.
 129 //#define HAL_ICACHE_LOCK(_base_, _size_)
 130
 131 // Undo a previous lock operation
 132 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
 133
 134 // Unlock entire cache
 135 //#define HAL_ICACHE_UNLOCK_ALL()
 136
 137 //-----------------------------------------------------------------------------
 138 // Instruction cache line control
 139
 140 // Invalidate cache lines in the given range without writing to memory.
 141 #define HAL_ICACHE_INVALIDATE( _base_ , _size_ )        \
 142 CYG_MACRO_START                                         \
 143     cyg_uint32 _b = _base_;                             \
 144     cyg_uint32 _s = _size_;                             \
 145     while (_s > HAL_DCACHE_LINE_SIZE) {                 \
 146         asm volatile ("ici @(%0,gr0)"                   \
 147                       :                                 \
 148                       : "r"(_b)                         \
 149             );                                          \
 150         _s -= HAL_DCACHE_LINE_SIZE;                     \
 151         _b += HAL_DCACHE_LINE_SIZE;                     \
 152     }                                                   \
 153 CYG_MACRO_END
 154
 155 //-----------------------------------------------------------------------------
 156 // Global control of data cache
 157
 158 // Enable the data cache
 159 #define HAL_DCACHE_ENABLE()                     \
 160 CYG_MACRO_START                                 \
 161     cyg_uint32 mask = _HSR0_DCE;                \
 162     asm volatile (                              \
 163         "movsg hsr0,gr4\n"                      \
 164         "\tor    gr4,%0,gr4\n"                  \
 165         "\tmovgs gr4,hsr0\n"                    \
 166         :                                       \
 167         : "r"(mask)                             \
 168         : "gr4" /* Clobber list */              \
 169         );                                      \
 170 CYG_MACRO_END
 171
 172 // Disable the data cache (and invalidate it, required semanitcs)
 173 #define HAL_DCACHE_DISABLE()                    \
 174 CYG_MACRO_START                                 \
 175     cyg_uint32 mask = ~_HSR0_DCE;               \
 176     asm volatile (                              \
 177         "movsg hsr0,gr4\n"                      \
 178         "\tand   gr4,%0,gr4\n"                  \
 179         "\tmovgs gr4,hsr0\n"                    \
 180         :                                       \
 181         : "r"(mask)                             \
 182         : "gr4" /* Clobber list */              \
 183         );                                      \
 184 CYG_MACRO_END
 185
 186 // Query the state of the data cache
 187 #define HAL_DCACHE_IS_ENABLED(_state_)          \
 188 CYG_MACRO_START                                 \
 189     register cyg_uint32 reg;                    \
 190     asm volatile ("movsg hsr0,%0"               \
 191                   : "=r"(reg)                   \
 192                   :                             \
 193         );                                      \
 194     (_state_) = (0 != (_HSR0_DCE & reg));       \
 195 CYG_MACRO_END
 196
 197 // Flush (invalidate) the entire dcache
 198 #define HAL_DCACHE_INVALIDATE_ALL()             \
 199 CYG_MACRO_START                                 \
 200     asm volatile ("dcei @(gr4,gr0),1"           \
 201                   :                             \
 202                   :                             \
 203         );                                      \
 204 CYG_MACRO_END
 205
 206 // Synchronize the contents of the cache with memory.
 207 #define HAL_DCACHE_SYNC()                       \
 208 CYG_MACRO_START                                 \
 209     asm volatile ("dcef @(gr4,gr0),1"           \
 210                   :                             \
 211                   :                             \
 212         );                                      \
 213 CYG_MACRO_END
 214
 215 // Set the data cache refill burst size
 216 //#define HAL_DCACHE_BURST_SIZE(_size_)
 217
 218 // Set the data cache write mode
 219 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 220
 221 #define HAL_DCACHE_WRITETHRU_MODE       0
 222 #define HAL_DCACHE_WRITEBACK_MODE       1
 223
 224 // Get the current writeback mode - or only writeback mode if fixed
 225 #define HAL_DCACHE_QUERY_WRITE_MODE( _mode_ ) CYG_MACRO_START           \
 226     _mode_ = HAL_DCACHE_WRITETHRU_MODE;                                 \
 227 CYG_MACRO_END
 228
 229 // Load the contents of the given address range into the data cache
 230 // and then lock the cache so that it stays there.
 231 //#define HAL_DCACHE_LOCK(_base_, _size_)
 232
 233 // Undo a previous lock operation
 234 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
 235
 236 // Unlock entire cache
 237 //#define HAL_DCACHE_UNLOCK_ALL()
 238
 239 //-----------------------------------------------------------------------------
 240 // Data cache line control
 241
 242 // Allocate cache lines for the given address range without reading its
 243 // contents from memory.
 244 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 245
 246 // Write dirty cache lines to memory and invalidate the cache entries
 247 // for the given address range.
 248 #define HAL_DCACHE_FLUSH( _base_ , _size_ )     \
 249 CYG_MACRO_START                                 \
 250     HAL_DCACHE_STORE( _base_ , _size_ );        \
 251     HAL_DCACHE_INVALIDATE( _base_ , _size_ );   \
 252 CYG_MACRO_END
 253
 254 // Invalidate cache lines in the given range without writing to memory.
 255 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ )        \
 256 CYG_MACRO_START                                         \
 257     cyg_uint32 _b = _base_;                             \
 258     cyg_uint32 _s = _size_;                             \
 259     while (_s > HAL_DCACHE_LINE_SIZE) {                 \
 260         asm volatile ("dci @(%0,gr0)"                   \
 261                       :                                 \
 262                       : "r"(_b)                         \
 263             );                                          \
 264         _s -= HAL_DCACHE_LINE_SIZE;                     \
 265         _b += HAL_DCACHE_LINE_SIZE;                     \
 266     }                                                   \
 267 CYG_MACRO_END
 268
 269 // Write dirty cache lines to memory for the given address range.
 270 #define HAL_DCACHE_STORE( _base_ , _size_ )     \
 271 CYG_MACRO_START                                 \
 272     cyg_uint32 _b = _base_;                     \
 273     cyg_uint32 _s = _size_;                     \
 274     while (_s > HAL_DCACHE_LINE_SIZE) {         \
 275         asm volatile ("dcf @(%0,gr0)"           \
 276                       :                         \
 277                       : "r"(_b)                 \
 278             );                                  \
 279         _s -= HAL_DCACHE_LINE_SIZE;             \
 280         _b += HAL_DCACHE_LINE_SIZE;             \
 281     }                                           \
 282 CYG_MACRO_END
 283
 284 // Preread the given range into the cache with the intention of reading
 285 // from it later.
 286 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
 287
 288 // Preread the given range into the cache with the intention of writing
 289 // to it later.
 290 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
 291
 292 // Allocate and zero the cache lines associated with the given range.
 293 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
 294
 295 //-----------------------------------------------------------------------------
 296
 297 #endif // ifndef CYGONCE_HAL_CACHE_H
 298 // End of hal_cache.h