1 #ifndef _CYGONCE_PLATFORM_INC_H_
2 #define _CYGONCE_PLATFORM_INC_H_
3 // #========================================================================
7 // # Fujitsu platform specific setups (assembler macros)
9 // #========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
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40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 // #========================================================================
43 // ######DESCRIPTIONBEGIN####
45 // # Author(s): gthomas
46 // # Contributors: gthomas
48 // # Purpose: Fujitsu (FRV400) platform specific setups
49 // # Description: This file defines various macros used by the generic
50 // # HAL startup code.
52 // #####DESCRIPTIONEND####
54 // #========================================================================
56 // Display a value in the system LEDs
58 sethi #(_FRV400_MB_LEDS>>16),gr15
59 setlo #(_FRV400_MB_LEDS&0xFFFF),gr15
65 // Platform initialization - only the necessary bits required to get the
66 // board started from a cold reset.
68 li 0x7FFF,gr4 // First, a good long spin
73 call 10f // position independent way to get @_platform_tab
78 .long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
79 .long _FRV400_SDRAM_AM0,0x0FF00000
84 .long _FRV400_LBUS_CR0,0x03010D01 // ROM/FLASH 0xFF000000..0xFFFFFFFF
85 // 16 bits wide, 13 wait states, 1 idle
87 .long _FRV400_LBUS_BR1,0x10000000 // PCI bridge 0x10000000..0x100FFFFF
88 .long _FRV400_LBUS_AM1,0x000FFFFF
89 .long _FRV400_LBUS_CR1,0x00000000
91 .long _FRV400_LBUS_BR2,0x20000000 // SRAM, FPGA, PCI 0x20000000..0x2FFFFFFF
92 .long _FRV400_LBUS_AM2,0x0FFFFFFF
93 .long _FRV400_LBUS_CR2,0x00000000
95 .long _FRV400_LBUS_BR3,0x00000000 // SDRAM?
96 .long _FRV400_LBUS_AM3,0xFFFFFFFF
97 .long _FRV400_LBUS_CR3,0x00000F07
99 .long _FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
100 .long _FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
102 .long _FRV400_SDRAM_CTL,0x05022000 // SDRAM mode/control
103 .long _FRV400_SDRAM_AN0,0x00010101
104 .long _FRV400_SDRAM_ART,0x00000820
105 .long _FRV400_SDRAM_RCN,0x00000000
106 .long _FRV400_SDRAM_MS, 0x00020200
107 .long _FRV400_SDRAM_CFG,0x80000000
109 //? .long _FRV400_CLK_CTRL,0x00000001 // External clock divisor (/2)
112 // PCI controller/bridge
114 .long _FRV400_PCI_SLBUS_CONFIG, 0x000800E2 // This matches the docs
115 // .long _FRV400_PCI_SLBUS_CONFIG, 0x000000E0 // This matches the samples
116 .long _FRV400_PCI_ECS0_CONFIG, 0x00000000
117 .long _FRV400_PCI_ECS1_CONFIG, 0x000003C1
118 .long _FRV400_PCI_ECS2_CONFIG, 0x000001C1
119 .long _FRV400_PCI_ECS0_RANGE, 0x00000000
120 .long _FRV400_PCI_ECS0_ADDR, 0x00000000
121 .long _FRV400_PCI_ECS1_RANGE, 0x00007FFE
122 .long _FRV400_PCI_ECS1_ADDR, 0x08108000
123 .long _FRV400_PCI_ECS2_RANGE, 0x00007FFE
124 .long _FRV400_PCI_ECS2_ADDR, 0x08100000
125 .long _FRV400_PCI_PCIIO_RANGE, 0x0001FFFE
126 .long _FRV400_PCI_PCIIO_ADDR, 0x00120000
127 .long _FRV400_PCI_PCIMEM_RANGE, 0x0003FFFE
128 .long _FRV400_PCI_PCIMEM_ADDR, 0x00140000
129 .long _FRV400_PCI_PCIIO_PCI_ADDR, 0x24000001
130 .long _FRV400_PCI_PCIMEM_PCI_ADDR, 0x28000000
131 .long _FRV400_MB_PCI_ARBITER, 0x00000001
132 .long _FRV400_MB_PCI_ARBITER, 0x00000001
134 .long _FRV400_PCI_SLBUS_CONFIG, 0x800800E2
135 // .long _FRV400_PCI_SLBUS_CONFIG, 0x800000E0
137 .long _FRV400_SDRAM_STS
139 10: movsg lr,gr4 // _platform_tab -> list of initializations
140 20: ldi @(gr4,0),gr5 // Register
141 ldi @(gr4,4),gr6 // Value
142 cmp gr5,gr0,icc0 // End of list?
147 30: ldi @(gr6,0),gr5 // gr6 == _FRV400_SDRAM_STS
149 bne icc0,0,30b // Wait for SDRAM ready
152 // Note: it is unclear from the documentation if this works at all. There is no
153 // description of how these registers are searched and what would happen if they
154 // overlap. If it turns out that they are not allowed to overlap, then this setup
155 // will have to be restructured.
157 li 0x03F0003D,gr4 // Set 0x03FXXXXX supervisor only, no cache - PCI window (1MB)
159 li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
161 li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
163 li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
166 li (1<<25),gr5 // Enable data MMU
172 #endif // _CYGONCE_PLATFORM_INC_H_