1 #ifndef CYGONCE_PLF_IO_H
2 #define CYGONCE_PLF_IO_H
4 //=============================================================================
8 // Platform specific IO support
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
46 // Author(s): hmt, jskov
47 // Contributors: hmt, jskov, gthomas
49 // Purpose: Fujitsu FR-V400 PCI IO support macros
51 // Usage: #include <cyg/hal/plf_io.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 #include CYGBLD_HAL_PLATFORM_H
58 #include CYGBLD_HAL_PLF_DEFS_H
60 #include <cyg/hal/hal_io.h> // IO macros
61 #include <cyg/hal/plf_ints.h> // Interrupt vectors
63 // Restrict device [slot] space
64 #define CYG_PCI_MAX_BUS 1 // Only one BUS
65 #define CYG_PCI_MIN_DEV 16 // Slots start at 16
66 #define CYG_PCI_MAX_DEV 21 // ... and end at 20
68 //-----------------------------------------------------------------------------
71 // Map PCI device resources starting from these addresses in PCI space.
72 #define HAL_PCI_ALLOC_BASE_MEMORY 0x28000000
73 #define HAL_PCI_ALLOC_BASE_IO 0x24000000
75 // This is where the PCI spaces are mapped in the CPU's address space.
76 #define HAL_PCI_PHYSICAL_MEMORY_BASE 0 // 0x28000000
77 #define HAL_PCI_PHYSICAL_IO_BASE 0 // 0x24000000
79 // These seem to be defined multiple ways?
80 #define CYGMEM_SECTION_pci_window 0x03F00000
81 #define CYGMEM_SECTION_pci_window_SIZE 0x00100000
82 #define CYGHWR_HAL_FRV_FRV400_PCI_MEM_MAP_BASE 0x03F00000
83 #define CYGHWR_HAL_FRV_FRV400_PCI_MEM_MAP_SIZE 0x00100000
85 // Initialize the PCI environment
86 externC void _frv400_pci_init(void);
87 #define HAL_PCI_INIT() \
90 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
91 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
92 externC void _frv400_pci_translate_interrupt(int bus, int devfn, int *vec, int *valid);
93 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid) \
94 _frv400_pci_translate_interrupt(__bus, __devfn, &__vec, &__valid)
96 // Read a value from the PCI configuration space of the appropriate
97 // size at an address composed from the bus, devfn and offset.
98 externC cyg_uint8 _frv400_pci_cfg_read_uint8(int bus, int dev, int offset);
99 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val ) \
100 __val = _frv400_pci_cfg_read_uint8(__bus, __devfn, __offset)
102 externC cyg_uint16 _frv400_pci_cfg_read_uint16(int bus, int dev, int offset);
103 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
104 __val = _frv400_pci_cfg_read_uint16(__bus, __devfn, __offset)
106 externC cyg_uint32 _frv400_pci_cfg_read_uint32(int bus, int dev, int offset);
107 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
108 __val = _frv400_pci_cfg_read_uint32(__bus, __devfn, __offset)
110 // Write a value to the PCI configuration space of the appropriate
111 // size at an address composed from the bus, devfn and offset.
112 externC void _frv400_pci_cfg_write_uint8(int bus, int dev, int offset, cyg_uint8 val);
113 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val ) \
114 _frv400_pci_cfg_write_uint8(__bus, __devfn, __offset, __val)
116 externC void _frv400_pci_cfg_write_uint16(int bus, int dev, int offset, cyg_uint16 val);
117 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
118 _frv400_pci_cfg_write_uint16(__bus, __devfn, __offset, __val)
120 externC void _frv400_pci_cfg_write_uint32(int bus, int dev, int offset, cyg_uint32 val);
121 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
122 _frv400_pci_cfg_write_uint32(__bus, __devfn, __offset, __val)
124 //-----------------------------------------------------------------------------
126 #endif // CYGONCE_PLF_IO_H