1 //==========================================================================
5 // HAL misc board support definitions for Fujitsu MB93091 (FR-V 400)
7 //==========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //==========================================================================
41 //#####DESCRIPTIONBEGIN####
44 // Contributors: gthomas
46 // Purpose: Platform register definitions
49 //####DESCRIPTIONEND####
51 //========================================================================*/
53 #ifndef __HAL_MB93091_H__
54 #define __HAL_MB93091_H__ 1
56 #include <cyg/hal/fr-v.h>
57 #include <cyg/hal/fr400.h>
58 #include <cyg/hal/fr500.h>
60 // PCI Bridge (on motherboard)
61 #define _MB93091_PCI_SLBUS_CONFIG 0x10000000
62 #define _MB93091_PCI_ECS0_CONFIG 0x10000008
63 #define _MB93091_PCI_ECS1_CONFIG 0x10000010
64 #define _MB93091_PCI_ECS2_CONFIG 0x10000018
65 #define _MB93091_PCI_ECS0_RANGE 0x10000020
66 #define _MB93091_PCI_ECS0_ADDR 0x10000028
67 #define _MB93091_PCI_ECS1_RANGE 0x10000030
68 #define _MB93091_PCI_ECS1_ADDR 0x10000038
69 #define _MB93091_PCI_ECS2_RANGE 0x10000040
70 #define _MB93091_PCI_ECS2_ADDR 0x10000048
71 #define _MB93091_PCI_PCIIO_RANGE 0x10000050
72 #define _MB93091_PCI_PCIIO_ADDR 0x10000058
73 #define _MB93091_PCI_PCIMEM_RANGE 0x10000060
74 #define _MB93091_PCI_PCIMEM_ADDR 0x10000068
75 #define _MB93091_PCI_PCIIO_PCI_ADDR 0x10000070
76 #define _MB93091_PCI_PCIMEM_PCI_ADDR 0x10000078
77 #define _MB93091_PCI_CONFIG_ADDR 0x10000080
78 #define _MB93091_PCI_CONFIG_DATA 0x10000088
80 #define _MB93091_PCI_SL_TO_PCI_MBX0 0x10000500
81 #define _MB93091_PCI_SL_TO_PCI_MBX1 0x10000508
82 #define _MB93091_PCI_SL_TO_PCI_MBX2 0x10000510
83 #define _MB93091_PCI_SL_TO_PCI_MBX3 0x10000518
84 #define _MB93091_PCI_SL_TO_PCI_MBX4 0x10000520
85 #define _MB93091_PCI_SL_TO_PCI_MBX5 0x10000528
86 #define _MB93091_PCI_SL_TO_PCI_MBX6 0x10000530
87 #define _MB93091_PCI_SL_TO_PCI_MBX7 0x10000538
88 #define _MB93091_PCI_PCI_TO_SL_MBX0 0x10000540
89 #define _MB93091_PCI_PCI_TO_SL_MBX1 0x10000548
90 #define _MB93091_PCI_PCI_TO_SL_MBX2 0x10000550
91 #define _MB93091_PCI_PCI_TO_SL_MBX3 0x10000558
92 #define _MB93091_PCI_PCI_TO_SL_MBX4 0x10000560
93 #define _MB93091_PCI_PCI_TO_SL_MBX5 0x10000568
94 #define _MB93091_PCI_PCI_TO_SL_MBX6 0x10000570
95 #define _MB93091_PCI_PCI_TO_SL_MBX7 0x10000578
96 #define _MB93091_PCI_MBX_STATUS 0x10000580
97 #define _MB93091_PCI_MBX_CONTROL 0x10000588
98 #define _MB93091_PCI_SL_TO_PCI_DOORBELL 0x10000590
99 #define _MB93091_PCI_PCI_TO_SL_DOORBELL 0x10000598
100 #define _MB93091_PCI_SL_INT_STATUS 0x100005A0
101 #define _MB93091_PCI_SL_INT_STATUS_MASTER_ABORT (1<<26)
102 #define _MB93091_PCI_PCI_INT_STATUS 0x100005A8
103 #define _MB93091_PCI_SL_INT_ENABLE 0x100005B0
104 #define _MB93091_PCI_PCI_INT_ENABLE 0x100005B8
106 #define _MB93091_PCI_CONFIG 0x10000800
107 #define _MB93091_PCI_DEVICE_VENDOR 0x10000800
108 #define _MB93091_PCI_STAT_CMD 0x10000808
109 #define _MB93091_PCI_STAT_ERROR_MASK 0xF000
110 #define _MB93091_PCI_CLASS_REV 0x10000810
111 #define _MB93091_PCI_BIST 0x10000818
112 #define _MB93091_PCI_PCI_IO_MAPPED 0x10000820
113 #define _MB93091_PCI_PCI_MEM_MAP_LO 0x10000828
114 #define _MB93091_PCI_PCI_ECS0_LO 0x10000838
115 #define _MB93091_PCI_PCI_ECS1_LO 0x10000840
116 #define _MB93091_PCI_PCI_ECS2_LO 0x10000848
117 #define _MB93091_PCI_MAX_LAT 0x10000878
118 #define _MB93091_PCI_TMO_RETRY 0x10000880
119 #define _MB93091_PCI_SERR_ENABLE 0x10000888
120 #define _MB93091_PCI_RESET 0x10000890
121 #define _MB93091_PCI_RESET_SRST 0x00000001 // Assert soft reset
122 #define _MB93091_PCI_PCI_MEM_MAP_HI 0x10000898
123 #define _MB93091_PCI_PCI_ECS0_HI 0x100008A8
124 #define _MB93091_PCI_PCI_ECS1_HI 0x100008B0
125 #define _MB93091_PCI_PCI_ECS2_HI 0x100008B8
127 // Motherboard resources
128 #define _MB93091_MB_SWGP 0x21200000 // General purpose switches
129 #define _MB93091_MB_LEDS 0x21200004 // LED array - 16 bits 0->on
130 #define _MB93091_MB_LCD 0x21200008 // LCD panel
131 #define _MB93091_MB_BOOT_MODE 0x21300004 // Boot mode register
132 #define _MB93091_MB_H_RESET 0x21300008 // Hardware reset
133 #define _MB93091_MB_CLKSW 0x2130000C // Clock settings
134 #define _MB93091_MB_PCI_ARBITER 0x21300014 // Enable PCI arbiter mode
136 #define LCD_D 0x000000ff /* LCD data bus */
137 #define LCD_RW 0x00000100 /* LCD R/W signal */
138 #define LCD_RS 0x00000200 /* LCD Register Select */
139 #define LCD_E 0x00000400 /* LCD Start Enable Signal */
141 #define LCD_CMD_CLEAR (LCD_E|0x001)
142 #define LCD_CMD_HOME (LCD_E|0x002)
143 #define LCD_CMD_CURSOR_INC (LCD_E|0x004)
144 #define LCD_CMD_SCROLL_INC (LCD_E|0x005)
145 #define LCD_CMD_CURSOR_DEC (LCD_E|0x006)
146 #define LCD_CMD_SCROLL_DEC (LCD_E|0x007)
147 #define LCD_CMD_OFF (LCD_E|0x008)
148 #define LCD_CMD_ON(CRSR,BLINK) (LCD_E|0x00c|(CRSR<<1)|BLINK)
149 #define LCD_CMD_CURSOR_MOVE_L (LCD_E|0x010)
150 #define LCD_CMD_CURSOR_MOVE_R (LCD_E|0x014)
151 #define LCD_CMD_DISPLAY_SHIFT_L (LCD_E|0x018)
152 #define LCD_CMD_DISPLAY_SHIFT_R (LCD_E|0x01c)
153 #define LCD_CMD_FUNCSET(DL,N,F) (LCD_E|0x020|(DL<<4)|(N<<3)|(F<<2))
154 #define LCD_CMD_SET_CG_ADDR(X) (LCD_E|0x040|X)
155 #define LCD_CMD_SET_DD_ADDR(X) (LCD_E|0x080|X)
156 #define LCD_CMD_READ_BUSY (LCD_E|LCD_RW)
157 #define LCD_DATA_WRITE(X) (LCD_E|LCD_RS|(X))
158 #define LCD_DATA_READ (LCD_E|LCD_RS|LCD_RW)
161 #define _MB93091_FPGA_CONTROL 0xFFC00000 // Access control for FPGA resources
162 #define _MB93091_FPGA_CONTROL_IRQ (1<<2) // Set to enable IRQ registers
163 #define _MB93091_FPGA_CONTROL_CS4 (1<<1) // Set to enable CS4 control regs
164 #define _MB93091_FPGA_CONTROL_CS5 (1<<0) // Set to enable CS5 control regs
165 #define _MB93091_FPGA_IRQ_MASK 0xFFC00004 // Set bits to 0 to allow interrupt
166 #define _MB93091_FPGA_IRQ_LEVELS 0xFFC00008 // 0=>active low, 1=>active high
167 #define _MB93091_FPGA_IRQ_REQUEST 0xFFC0000C // read: 1=>asserted, write: 0=>clears
168 #define _MB93091_FPGA_IRQ_LAN (1<<12) // Onboard LAN controller
169 #define _MB93091_FPGA_IRQ_INTA (1<<6) // PCI bus INTA
170 #define _MB93091_FPGA_IRQ_INTB (1<<5) // PCI bus INTA
171 #define _MB93091_FPGA_IRQ_INTC (1<<4) // PCI bus INTA
172 #define _MB93091_FPGA_IRQ_INTD (1<<3) // PCI bus INTA
174 #define _MB93091_FPGA_GPHL 0xFFC00030 // CB70: GPH and GPL DIP-SW
175 #define _MB93091_FPGA_CLKRS 0xFFC00104 // For MB93091-CB70, setting of rotary switches
176 #define _MB93091_FPGA_VDKID 0xFFC001A0
178 #endif /* __HAL_MB93091_H__ */