1 #ifndef _CYGONCE_PLATFORM_INC_H_
2 #define _CYGONCE_PLATFORM_INC_H_
3 // #========================================================================
7 // # Fujitsu platform specific setups (assembler macros)
9 // #========================================================================
10 //####ECOSGPLCOPYRIGHTBEGIN####
11 // -------------------------------------------
12 // This file is part of eCos, the Embedded Configurable Operating System.
13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 // eCos is free software; you can redistribute it and/or modify it under
16 // the terms of the GNU General Public License as published by the Free
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20 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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26 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 // As a special exception, if other files instantiate templates or use macros
29 // or inline functions from this file, or you compile this file and link it
30 // with other works to produce a work based on this file, this file does not
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32 // License. However the source code for this file must still be made available
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39 // at http://sources.redhat.com/ecos/ecos-license/
40 // -------------------------------------------
41 //####ECOSGPLCOPYRIGHTEND####
42 // #========================================================================
43 // ######DESCRIPTIONBEGIN####
45 // # Author(s): gthomas
46 // # Contributors: gthomas
48 // # Purpose: Fujitsu (FRV400) platform specific setups
49 // # Description: This file defines various macros used by the generic
50 // # HAL startup code.
52 // #####DESCRIPTIONEND####
54 // #========================================================================
56 // Display a value in the system LEDs
58 sethi #(_MB93093_FPGA_LEDS>>16),gr15
59 setlo #(_MB93093_FPGA_LEDS&0xFFFF),gr15
64 // Platform initialization - only the necessary bits required to get the
65 // board started from a cold reset.
67 li 0x7FFF,gr4 // First, a good long spin
74 call 10f // position independent way to get @_platform_tab
77 // SDRAM setups for FR4xx
79 .long _FRV400_SDRAM_BR0,0x00000000 // SDRAM 0x0XXXXXXX
80 .long _FRV400_SDRAM_AM0,0x03FFFFFF
83 // LOCAL bus setups for FR4xx
85 .long _FRV400_LBUS_GCR,0x0000007f
86 .long _FRV400_LBUS_CR0,0x00010701 // ROM/FLASH 0xFF000000..0xFFFFFFFF
88 .long _FRV400_LBUS_BR1,0x10000000 // Ethernet
89 .long _FRV400_LBUS_AM1,0x0FFFFFFF
90 .long _FRV400_LBUS_CR1,0x00010404
92 .long _FRV400_LBUS_BR2,0x20000000 // FPGA
93 .long _FRV400_LBUS_AM2,0x0FFFFFFF
94 .long _FRV400_LBUS_CR2,0x00000000
96 .long _FRV400_LBUS_BR3,0x30000000 // CSR / CSC (MB93493)
97 .long _FRV400_LBUS_AM3,0x07FFFFFF
98 .long _FRV400_LBUS_CR3,0xc8100000
100 .long _FRV400_LBUS_BR4,0xfd000000
101 .long _FRV400_LBUS_AM4,0x00FFFFFF
102 .long _FRV400_LBUS_CR4,0x00010701
104 .long _FRV400_LBUS_BR5,0x38000000
105 .long _FRV400_LBUS_AM5,0x07FFFFFF
106 .long _FRV400_LBUS_CR5,0x00010000
108 .long _FRV400_LBUS_EST,0x00000000
109 .long _FRV400_LBUS_EAD,0x00000000
111 .long _FRV400_GPIO_SIR,0x000c954f // Routing for Rx0, Rx1, CTS
112 .long _FRV400_GPIO_SOR,0x00036ab0 // Routing for Tx0, Tx1, RTS, TOUT0, TOUT1
113 .long 0x20000020,0x55555555
114 .long _FRV400_SDRAM_CTL,0x05011000 // SDRAM mode/control
115 .long _FRV400_SDRAM_AN0,0x00010201
116 .long _FRV400_SDRAM_ART,0x00000820
117 .long _FRV400_SDRAM_RCN,0x00000000
118 .long _FRV400_SDRAM_MS, 0x00010000
119 .long _FRV400_SDRAM_CFG,0x80000100
121 //? .long _FRV400_CLK_CTRL,0x00000001 // External clock divisor (/2)
123 .long _FRV400_SDRAM_STS
128 10: movsg lr,gr4 // _platform_tab -> list of initializations
129 20: ldi @(gr4,0),gr5 // Register
130 ldi @(gr4,4),gr6 // Value
131 cmp gr5,gr0,icc0 // End of list?
136 30: ldi @(gr6,0),gr5 // gr6 == _FRVxxx_SDRAM_STS
138 bne icc0,0,30b // Wait for SDRAM ready
140 // Note: it is unclear from the documentation if this works at all. There is no
141 // description of how these registers are searched and what would happen if they
142 // overlap. If it turns out that they are not allowed to overlap, then this setup
143 // will have to be restructured.
146 // Clear all AMPR registers. They must not overlap.
174 li 0x03F0003D,gr4 // Set 0x03FXXXXX supervisor only, no cache - PCI window (1MB)
177 li 0x000000C9,gr4 // Set 0x0XXXXXXX supervisor only, cache - SDRAM
180 li 0x200000BD,gr4 // Set 0x2XXXXXXX supervisor only, no cache - Motherboard resources
183 li 0x100000BD,gr4 // Set 0x1XXXXXXX supervisor only, no cache - PCI bridge
187 li (1<<25),gr5 // Enable data MMU
193 #endif // _CYGONCE_PLATFORM_INC_H_