1 //=============================================================================
5 // Simple driver for the H8/300H Serial Communication Interface (SCI)
7 //=============================================================================
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40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
46 // Description: Simple driver for the H8/300H Serial Communication Interface
47 // Clients of this file can configure the behavior with:
48 // CYGNUM_SCI_PORTS: number of SCI ports
50 //####DESCRIPTIONEND####
52 //=============================================================================
54 #include <pkgconf/hal.h>
56 #ifdef CYGNUM_HAL_H8300_SCI_PORTS
58 #include <cyg/hal/hal_io.h> // IO macros
59 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
60 #include <cyg/hal/hal_misc.h> // Helper functions
61 #include <cyg/hal/hal_intr.h> // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
62 #include <cyg/hal/hal_arch.h> // SAVE/RESTORE GP
63 #include <cyg/hal/hal_if.h> // Calling-if API
64 #include <cyg/hal/mod_regs_sci.h> // serial register definitions
66 #include <cyg/hal/h8_sci.h> // our header
68 //--------------------------------------------------------------------------
71 cyg_hal_plf_sci_init_channel(void* chan)
74 cyg_uint8* base = ((channel_data_t *)chan)->base;
76 // Disable Tx/Rx interrupts, but enable Tx/Rx
77 HAL_WRITE_UINT8(base+_REG_SCSCR,
78 CYGARC_REG_SCSCR_TE|CYGARC_REG_SCSCR_RE);
81 HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
83 // Set speed to CYGNUM_HAL_H8300_H8300H_SCI_DEFAULT_BAUD_RATE
84 HAL_READ_UINT8(base+_REG_SCSMR, tmp);
85 tmp &= ~CYGARC_REG_SCSMR_CKSx_MASK;
86 tmp |= CYGARC_SCBRR_CKSx(CYGNUM_HAL_H8300_H8300H_SCI_BAUD_RATE);
87 HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
88 HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(CYGNUM_HAL_H8300_H8300H_SCI_BAUD_RATE));
92 cyg_hal_plf_sci_getc_nonblock(void* __ch_data, cyg_uint8* ch)
94 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
97 HAL_READ_UINT8(base+_REG_SCSSR, sr);
98 if (sr & CYGARC_REG_SCSSR_ORER) {
99 // Serial RX overrun. Clear error and let caller try again.
100 HAL_WRITE_UINT8(base+_REG_SCSSR,
101 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
105 if ((sr & CYGARC_REG_SCSSR_RDRF) == 0)
108 HAL_READ_UINT8(base+_REG_SCRDR, *ch);
110 // Clear buffer full flag.
111 HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_RDRF);
117 cyg_hal_plf_sci_getc(void* __ch_data)
120 CYGARC_HAL_SAVE_GP();
122 while(!cyg_hal_plf_sci_getc_nonblock(__ch_data, &ch));
124 CYGARC_HAL_RESTORE_GP();
129 cyg_hal_plf_sci_putc(void* __ch_data, cyg_uint8 c)
131 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
133 CYGARC_HAL_SAVE_GP();
136 HAL_READ_UINT8(base+_REG_SCSSR, sr);
137 } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
139 HAL_WRITE_UINT8(base+_REG_SCTDR, c);
142 HAL_WRITE_UINT8(base+_REG_SCSSR, sr & ~CYGARC_REG_SCSSR_TDRE);
144 // Hang around until the character has been safely sent.
146 HAL_READ_UINT8(base+_REG_SCSSR, sr);
147 } while ((sr & CYGARC_REG_SCSSR_TDRE) == 0);
149 CYGARC_HAL_RESTORE_GP();
153 static channel_data_t channels[CYGNUM_HAL_H8300_SCI_PORTS];
156 cyg_hal_plf_sci_write(void* __ch_data, const cyg_uint8* __buf,
159 CYGARC_HAL_SAVE_GP();
162 cyg_hal_plf_sci_putc(__ch_data, *__buf++);
164 CYGARC_HAL_RESTORE_GP();
168 cyg_hal_plf_sci_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
170 CYGARC_HAL_SAVE_GP();
173 *__buf++ = cyg_hal_plf_sci_getc(__ch_data);
175 CYGARC_HAL_RESTORE_GP();
179 cyg_hal_plf_sci_getc_timeout(void* __ch_data, cyg_uint8* ch)
181 channel_data_t* chan = (channel_data_t*)__ch_data;
184 CYGARC_HAL_SAVE_GP();
186 delay_count = chan->msec_timeout * 20; // delay in .1 ms steps
189 res = cyg_hal_plf_sci_getc_nonblock(__ch_data, ch);
190 if (res || 0 == delay_count--)
193 CYGACC_CALL_IF_DELAY_US(50);
196 CYGARC_HAL_RESTORE_GP();
201 cyg_hal_plf_sci_control(void *__ch_data, __comm_control_cmd_t __func, ...)
203 static int irq_state = 0;
204 channel_data_t* chan = (channel_data_t*)__ch_data;
207 CYGARC_HAL_SAVE_GP();
210 case __COMMCTL_IRQ_ENABLE:
212 HAL_INTERRUPT_UNMASK(chan->isr_vector);
213 HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
214 scr |= CYGARC_REG_SCSCR_RIE;
215 HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
217 case __COMMCTL_IRQ_DISABLE:
220 HAL_INTERRUPT_UNMASK(chan->isr_vector);
221 HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
222 scr &= ~CYGARC_REG_SCSCR_RIE;
223 HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
225 case __COMMCTL_DBG_ISR_VECTOR:
226 ret = chan->isr_vector;
228 case __COMMCTL_SET_TIMEOUT:
232 va_start(ap, __func);
234 ret = chan->msec_timeout;
235 chan->msec_timeout = va_arg(ap, cyg_uint32);
242 CYGARC_HAL_RESTORE_GP();
247 cyg_hal_plf_sci_isr(void *__ch_data, int* __ctrlc,
248 CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
251 cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
253 CYGARC_HAL_SAVE_GP();
256 HAL_READ_UINT8(base+_REG_SCSSR, sr);
257 if (sr & CYGARC_REG_SCSSR_ORER) {
258 // Serial RX overrun. Clear error and hope protocol recovers.
259 HAL_WRITE_UINT8(base+_REG_SCSSR,
260 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_ORER);
261 res = CYG_ISR_HANDLED;
262 } else if (sr & CYGARC_REG_SCSSR_RDRF) {
263 // Received character
264 HAL_READ_UINT8(base+_REG_SCRDR, c);
266 // Clear buffer full flag.
267 HAL_WRITE_UINT8(base+_REG_SCSSR,
268 CYGARC_REG_SCSSR_CLEARMASK & ~CYGARC_REG_SCSSR_RDRF);
270 if( cyg_hal_is_break( &c , 1 ) )
273 res = CYG_ISR_HANDLED;
276 CYGARC_HAL_RESTORE_GP();
281 cyg_hal_plf_sci_init(int sci_index, int comm_index,
282 int rcv_vect, cyg_uint8* base)
284 channel_data_t* chan = &channels[sci_index];
285 hal_virtual_comm_table_t* comm;
286 int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
288 // Initialize channel table
290 chan->isr_vector = rcv_vect;
291 chan->msec_timeout = 1000;
293 // Disable interrupts.
294 HAL_INTERRUPT_MASK(chan->isr_vector);
298 cyg_hal_plf_sci_init_channel(chan);
300 // Setup procs in the vector table
302 // Initialize channel procs
303 CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index);
304 comm = CYGACC_CALL_IF_CONSOLE_PROCS();
305 CYGACC_COMM_IF_CH_DATA_SET(*comm, chan);
306 CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_sci_write);
307 CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_sci_read);
308 CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_sci_putc);
309 CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_sci_getc);
310 CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_sci_control);
311 CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_sci_isr);
312 CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_sci_getc_timeout);
314 // Restore original console
315 CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
318 #endif // CYGNUM_HAL_H8300_H8300H_SCI_PORTS
320 //-----------------------------------------------------------------------------