packages/hal/h8300/h8s/v2_0/include/var_intr.h

   1 #ifndef CYGONCE_HAL_VAR_INTR_H
   2 #define CYGONCE_HAL_VAR_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      var_intr.h
   7 //
   8 //      H8S Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    yoshinori sato
  47 // Contributors: yoshinori sato
  48 // Date:         2003-01-01
  49 // Purpose:      H8S Interrupt Support
  50 // Description:  The macros defined here provide the HAL APIs for handling
  51 //               interrupts and the clock for H8/300H variants of the H8/300
  52 //               architecture.
  53 //
  54 // Usage:
  55 //              #include <cyg/hal/var_intr.h>
  56 //              ...
  57 //
  58 //
  59 //####DESCRIPTIONEND####
  60 //
  61 //==========================================================================
  62
  63 #include <pkgconf/hal.h>
  64
  65 #include <cyg/infra/cyg_type.h>
  66
  67 #include <cyg/hal/plf_intr.h>
  68 #include <cyg/hal/var_arch.h>
  69
  70 //--------------------------------------------------------------------------
  71 // Interrupt vectors.
  72
  73 // The level-specific hardware vectors
  74 // These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
  75 #define CYGNUM_HAL_VECTOR_RESET_P              0
  76 #define CYGNUM_HAL_VECTOR_RESET_M              1
  77 #define CYGNUM_HAL_VECTOR_RSV2                 2
  78 #define CYGNUM_HAL_VECTOR_RSV3                 3
  79 #define CYGNUM_HAL_VECTOR_RSV4                 4
  80 #define CYGNUM_HAL_VECTOR_TRACE                5
  81 #define CYGNUM_HAL_VECTOR_DIRECT               6
  82 #define CYGNUM_HAL_VECTOR_NMI                  7
  83 #define CYGNUM_HAL_VECTOR_TRAP0                8
  84 #define CYGNUM_HAL_VECTOR_TRAP1                9
  85 #define CYGNUM_HAL_VECTOR_TRAP2                10
  86 #define CYGNUM_HAL_VECTOR_TRAP3                11
  87
  88 #define CYGNUM_HAL_VSR_MIN                     0
  89 #define CYGNUM_HAL_VSR_MAX                     11
  90 #define CYGNUM_HAL_VSR_COUNT                   12
  91
  92 // Exception numbers. These are the values used when passed out to an
  93 // external exception handler using cyg_hal_deliver_exception()
  94
  95 #define CYGNUM_HAL_EXCEPTION_NMI               CYGNUM_HAL_VECTOR_NMI
  96
  97 #if 0
  98 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS       0
  99 #endif
 100
 101 #define CYGNUM_HAL_EXCEPTION_MIN               CYGNUM_HAL_VSR_MIN
 102 #define CYGNUM_HAL_EXCEPTION_MAX               CYGNUM_HAL_VSR_MAX
 103 #define CYGNUM_HAL_EXCEPTION_COUNT             CYGNUM_HAL_VSR_COUNT
 104
 105 // The decoded interrupts
 106 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0        16
 107 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1        17
 108 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2        18
 109 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3        19
 110 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4        20
 111 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5        21
 112 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6        22
 113 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7        23
 114 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_8        24
 115 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_9        25
 116 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_10       26
 117 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_11       27
 118 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_12       28
 119 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_13       29
 120 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_14       30
 121 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_15       31
 122
 123 #define CYGNUM_HAL_INTERRUPT_DTC               32
 124 #define CYGNUM_HAL_INTERRUPT_WDT               33
 125 #define CYGNUM_HAL_INTERRUPT_RSV34             34
 126 #define CYGNUM_HAL_INTERRUPT_RFSHCMI           35
 127 #define CYGNUM_HAL_INTERRUPT_RSV36             36
 128 #define CYGNUM_HAL_INTERRUPT_RSV37             37
 129 #define CYGNUM_HAL_INTERRUPT_ADI               38
 130 #define CYGNUM_HAL_INTERRUPT_RSV39             39
 131
 132 #define CYGNUM_HAL_INTERRUPT_TGI0A             40
 133 #define CYGNUM_HAL_INTERRUPT_TGI0B             41
 134 #define CYGNUM_HAL_INTERRUPT_TGI0C             42
 135 #define CYGNUM_HAL_INTERRUPT_TGI0D             43
 136 #define CYGNUM_HAL_INTERRUPT_TGI0V             44
 137 #define CYGNUM_HAL_INTERRUPT_RSV45             45
 138 #define CYGNUM_HAL_INTERRUPT_RSV46             46
 139 #define CYGNUM_HAL_INTERRUPT_RSV47             47
 140
 141 #define CYGNUM_HAL_INTERRUPT_TGI1A             48
 142 #define CYGNUM_HAL_INTERRUPT_TGI1B             49
 143 #define CYGNUM_HAL_INTERRUPT_TGI1V             50
 144 #define CYGNUM_HAL_INTERRUPT_TGI1U             51
 145
 146 #define CYGNUM_HAL_INTERRUPT_TGI2A             52
 147 #define CYGNUM_HAL_INTERRUPT_TGI2B             53
 148 #define CYGNUM_HAL_INTERRUPT_TGI2V             54
 149 #define CYGNUM_HAL_INTERRUPT_TGI2U             55
 150
 151 #define CYGNUM_HAL_INTERRUPT_TGI3A             56
 152 #define CYGNUM_HAL_INTERRUPT_TGI3B             57
 153 #define CYGNUM_HAL_INTERRUPT_TGI3C             58
 154 #define CYGNUM_HAL_INTERRUPT_TGI3D             59
 155 #define CYGNUM_HAL_INTERRUPT_TGI3V             60
 156 #define CYGNUM_HAL_INTERRUPT_RSV61             61
 157 #define CYGNUM_HAL_INTERRUPT_RSV62             62
 158 #define CYGNUM_HAL_INTERRUPT_RSV63             63
 159
 160 #define CYGNUM_HAL_INTERRUPT_TGI4A             64
 161 #define CYGNUM_HAL_INTERRUPT_TGI4B             65
 162 #define CYGNUM_HAL_INTERRUPT_TGI4V             66
 163 #define CYGNUM_HAL_INTERRUPT_TGI4U             67
 164
 165 #define CYGNUM_HAL_INTERRUPT_TGI5A             68
 166 #define CYGNUM_HAL_INTERRUPT_TGI5B             69
 167 #define CYGNUM_HAL_INTERRUPT_TGI5V             70
 168 #define CYGNUM_HAL_INTERRUPT_TGI5U             71
 169
 170 #define CYGNUM_HAL_INTERRUPT_CMIA0             72
 171 #define CYGNUM_HAL_INTERRUPT_CMIB0             73
 172 #define CYGNUM_HAL_INTERRUPT_OVI0              74
 173 #define CYGNUM_HAL_INTERRUPT_RSV75             75
 174
 175 #define CYGNUM_HAL_INTERRUPT_CMIA1             76
 176 #define CYGNUM_HAL_INTERRUPT_CMIB1             77
 177 #define CYGNUM_HAL_INTERRUPT_OVI1              78
 178 #define CYGNUM_HAL_INTERRUPT_RSV79             79
 179
 180 #define CYGNUM_HAL_INTERRUPT_DEND0A            80
 181 #define CYGNUM_HAL_INTERRUPT_DEND0B            81
 182 #define CYGNUM_HAL_INTERRUPT_DEND1A            82
 183 #define CYGNUM_HAL_INTERRUPT_DEND1B            83
 184
 185 #define CYGNUM_HAL_INTERRUPT_EXDEND0           84
 186 #define CYGNUM_HAL_INTERRUPT_EXDEND1           85
 187 #define CYGNUM_HAL_INTERRUPT_EXDEND2           86
 188 #define CYGNUM_HAL_INTERRUPT_EXDEND3           87
 189
 190 #define CYGNUM_HAL_INTERRUPT_ERI0              88
 191 #define CYGNUM_HAL_INTERRUPT_RXI0              89
 192 #define CYGNUM_HAL_INTERRUPT_TXI0              90
 193 #define CYGNUM_HAL_INTERRUPT_TEI0              91
 194
 195 #define CYGNUM_HAL_INTERRUPT_ERI1              92
 196 #define CYGNUM_HAL_INTERRUPT_RXI1              93
 197 #define CYGNUM_HAL_INTERRUPT_TXI1              94
 198 #define CYGNUM_HAL_INTERRUPT_TEI1              95
 199
 200 #define CYGNUM_HAL_INTERRUPT_ERI2              96
 201 #define CYGNUM_HAL_INTERRUPT_RXI2              97
 202 #define CYGNUM_HAL_INTERRUPT_TXI2              98
 203 #define CYGNUM_HAL_INTERRUPT_TEI2              99
 204
 205 #define CYGNUM_HAL_INTERRUPT_RSV100            100
 206 #define CYGNUM_HAL_INTERRUPT_RSV101            101
 207 #define CYGNUM_HAL_INTERRUPT_RSV102            102
 208 #define CYGNUM_HAL_INTERRUPT_RSV103            103
 209 #define CYGNUM_HAL_INTERRUPT_RSV104            104
 210 #define CYGNUM_HAL_INTERRUPT_RSV105            105
 211 #define CYGNUM_HAL_INTERRUPT_RSV106            106
 212 #define CYGNUM_HAL_INTERRUPT_RSV107            107
 213 #define CYGNUM_HAL_INTERRUPT_RSV108            108
 214 #define CYGNUM_HAL_INTERRUPT_RSV109            109
 215 #define CYGNUM_HAL_INTERRUPT_RSV110            110
 216 #define CYGNUM_HAL_INTERRUPT_RSV111            111
 217 #define CYGNUM_HAL_INTERRUPT_RSV112            112
 218 #define CYGNUM_HAL_INTERRUPT_RSV113            113
 219 #define CYGNUM_HAL_INTERRUPT_RSV114            114
 220 #define CYGNUM_HAL_INTERRUPT_RSV115            115
 221 #define CYGNUM_HAL_INTERRUPT_RSV116            116
 222 #define CYGNUM_HAL_INTERRUPT_RSV117            117
 223 #define CYGNUM_HAL_INTERRUPT_RSV118            118
 224 #define CYGNUM_HAL_INTERRUPT_RSV119            119
 225 #define CYGNUM_HAL_INTERRUPT_RSV120            120
 226 #define CYGNUM_HAL_INTERRUPT_RSV121            121
 227 #define CYGNUM_HAL_INTERRUPT_RSV122            122
 228 #define CYGNUM_HAL_INTERRUPT_RSV123            123
 229 #define CYGNUM_HAL_INTERRUPT_RSV124            124
 230 #define CYGNUM_HAL_INTERRUPT_RSV125            125
 231 #define CYGNUM_HAL_INTERRUPT_RSV126            126
 232 #define CYGNUM_HAL_INTERRUPT_RSV127            127
 233
 234
 235 #define CYGNUM_HAL_ISR_MIN                     16
 236 #define CYGNUM_HAL_ISR_MAX                     127
 237
 238 #define CYGNUM_HAL_ISR_COUNT                   (3+((CYGNUM_HAL_ISR_MAX+1)/4))
 239
 240 // The vector used by the Real time clock
 241
 242 #define CYGNUM_HAL_INTERRUPT_RTC                CYGNUM_HAL_INTERRUPT_CMIA1
 243
 244 //--------------------------------------------------------------------------
 245 // Interrupt vector translation.
 246
 247 #if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 248
 249 #define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
 250               _index_ = (_vector_)
 251
 252 #endif
 253
 254 //--------------------------------------------------------------------------
 255 // H8/300H specific version of HAL_INTERRUPT_CONFIGURE
 256
 257 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )                \
 258         hal_interrupt_configure( _vector_, _level_, _up_ )
 259
 260 externC void hal_interrupt_configure(int vector,int level,int up);
 261
 262 #define HAL_INTERRUPT_CONFIGURE_DEFINED
 263
 264 //--------------------------------------------------------------------------
 265 // Interrupt control macros
 266
 267 #define HAL_DISABLE_INTERRUPTS(_old_)   \
 268         asm volatile (                  \
 269             "sub.l er0,er0\n\t"         \
 270             "stc exr,r0l\n\t"           \
 271             "orc #0x7,exr\n\t"          \
 272             "and.b #0x07,r0l\n\t"       \
 273             "mov.l er0,%0"              \
 274             : "=r"(_old_)               \
 275             :                           \
 276             : "er0"                     \
 277             );
 278
 279 #define HAL_ENABLE_INTERRUPTS()         \
 280         asm volatile (                  \
 281             "andc #0xf8,exr"            \
 282             );
 283
 284 #define HAL_RESTORE_INTERRUPTS(_old_)   \
 285         asm volatile (                  \
 286             "mov.l %0,er0\n\t"          \
 287             "and.b #0x07,r0l\n\t"       \
 288             "stc exr,r0h\n\t"           \
 289             "and.b #0xf8,r0h\n\t"       \
 290             "or.b r0h,r0l\n\t"          \
 291             "ldc r0l,exr"               \
 292             :                           \
 293             : "r"(_old_)                \
 294             : "er0"                     \
 295             );
 296
 297 #define HAL_QUERY_INTERRUPTS(_old_)     \
 298         asm volatile (                  \
 299             "sub.l er0,er0\n\t"         \
 300             "stc exr,r0l\n\t"           \
 301             "and.b #0x07,r0l\n\t"       \
 302             "mov.l er0,%0"              \
 303             : "=r"(_old_)               \
 304             );
 305
 306 //--------------------------------------------------------------------------
 307 // Clock control.
 308
 309 externC void hal_clock_initialize(cyg_uint32 period);
 310 externC void hal_clock_reset(cyg_uint32 vector,cyg_uint32 period);
 311 externC void hal_clock_read(cyg_uint32 *pvalue);
 312
 313 #define HAL_CLOCK_INITIALIZE( _period_ ) \
 314         hal_clock_initialize( _period_ )
 315
 316 #define HAL_CLOCK_RESET( _vector_, _period_ ) \
 317         hal_clock_reset( _vector_, _period_ )
 318
 319 #define HAL_CLOCK_READ( _pvalue_ ) \
 320         hal_clock_read( _pvalue_ )
 321
 322 // FIXME: above line should not use CYGNUM_KERNEL_COUNTERS_RTC_PERIOD since
 323 // this means the HAL gets configured by kernel options even when the
 324 // kernel is disabled!
 325
 326
 327 //--------------------------------------------------------------------------
 328 #endif // ifndef CYGONCE_HAL_VAR_INTR_H
 329 // End of var_intr.h