1 # ====================================================================
3 # hal_h8300_h8300h_sim.cdl
5 # H8/300H SIM HAL package configuration data
7 # ====================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
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27 ## or inline functions from this file, or you compile this file and link it
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38 ## -------------------------------------------
39 #####ECOSGPLCOPYRIGHTEND####
40 # ====================================================================
41 ######DESCRIPTIONBEGIN####
44 # Original data: bartv
48 #####DESCRIPTIONEND####
50 # ====================================================================
52 cdl_package CYGPKG_HAL_H8300_H8300H_SIM {
53 display "H8/300H simulator"
54 parent CYGPKG_HAL_H8300
55 requires CYGPKG_HAL_H8300_H8300H
56 implements CYGINT_HAL_VIRTUAL_VECTOR_SUPPORT
57 implements CYGINT_HAL_DEBUG_GDB_STUBS
58 implements CYGINT_HAL_DEBUG_GDB_STUBS_BREAK
59 define_header hal_h8300_h8300h_sim.h
62 The minimal simulator HAL package is provided for use when
63 only a simple simulation of the processor architecture is
64 desired, as opposed to detailed simulation of any specific
65 board. In particular it is not possible to simulate any of
66 the I/O devices, so device drivers cannot be used."
68 compile hal_diag.c plf_misc.c delay_us.S
71 puts $::cdl_system_header "#define CYGBLD_HAL_TARGET_H <pkgconf/hal_h8300_h8300h.h>"
72 puts $::cdl_system_header "#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_h8300_h8300h_sim.h>"
74 puts $::cdl_header "#define CYG_HAL_H8300"
75 puts $::cdl_header "#define CYGNUM_HAL_H8300_SCI_PORTS 1"
76 puts $::cdl_header "#define CYGHWR_HAL_VECTOR_TABLE 0xfff000"
79 cdl_component CYG_HAL_STARTUP {
80 display "Startup type"
85 define -file system.h CYG_HAL_STARTUP
87 Only supports RAM startup."
90 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS {
91 display "Number of communication channels on the board"
96 cdl_option CYGNUM_HAL_VIRTUAL_VECTOR_DEBUG_CHANNEL {
97 display "Debug serial port"
99 legal_values 0 to CYGNUM_HAL_VIRTUAL_VECTOR_COMM_CHANNELS-1
102 The CQ/7708 board has only one serial port. This option
103 chooses which port will be used to connect to a host
107 # Real-time clock/counter specifics
108 cdl_component CYGNUM_HAL_RTC_CONSTANTS {
109 display "Real-time clock constants."
112 cdl_option CYGNUM_HAL_RTC_NUMERATOR {
113 display "Real-time clock numerator"
115 default_value 1000000000
117 cdl_option CYGNUM_HAL_RTC_DENOMINATOR {
118 display "Real-time clock denominator"
122 cdl_option CYGNUM_HAL_H8300_RTC_PRESCALE {
123 display "Real-time clock base prescale"
127 # Isn't a nice way to handle freq requirement!
128 cdl_option CYGNUM_HAL_RTC_PERIOD {
129 display "Real-time clock period"
135 cdl_option CYGHWR_HAL_H8300_CPG_INPUT {
136 display "OSC/Clock Freqency"
138 default_value 8000000
141 cdl_component CYGBLD_GLOBAL_OPTIONS {
142 display "Global build options"
146 Global build options including control over
147 compiler flags, linker flags and choice of toolchain."
150 cdl_option CYGBLD_GLOBAL_COMMAND_PREFIX {
151 display "Global command prefix"
154 default_value { "h8300-elf" }
156 This option specifies the command prefix used when
157 invoking the build tools."
160 cdl_option CYGBLD_GLOBAL_CFLAGS {
161 display "Global compiler flags"
164 default_value { "-Wall -Wpointer-arith -Wstrict-prototypes -Winline -Wundef -Woverloaded-virtual -g -O2 -mh -mint32 -fsigned-char -fdata-sections -fno-rtti -fno-exceptions -fvtable-gc -finit-priority" }
166 This option controls the global compiler flags which
167 are used to compile all packages by
168 default. Individual packages may define
169 options which override these global flags."
172 cdl_option CYGBLD_GLOBAL_LDFLAGS {
173 display "Global linker flags"
176 default_value { "-g -nostdlib -Wl,--gc-sections -Wl,-static -mrelax -mh -mint32" }
178 This option controls the global linker flags. Individual
179 packages may define options which override these global flags."
183 cdl_component CYGHWR_MEMORY_LAYOUT {
184 display "Memory layout"
187 calculated { "h8300_h8300h_sim_ram" }
189 cdl_option CYGHWR_MEMORY_LAYOUT_LDI {
190 display "Memory layout linker script fragment"
193 define -file system.h CYGHWR_MEMORY_LAYOUT_LDI
194 calculated { "<pkgconf/mlt_h8300_h8300h_sim_ram.ldi>" }
197 cdl_option CYGHWR_MEMORY_LAYOUT_H {
198 display "Memory layout header file"
201 define -file system.h CYGHWR_MEMORY_LAYOUT_H
202 calculated { "<pkgconf/mlt_h8300_h8300h_sim_ram.h>" }
205 cdl_option CYGHAL_PLF_SCI_BASE {
206 display "SCI Base address"
208 default_value 0xffffb0
210 Used SCI Channel base address."