packages/hal/mips/mips64/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_IMP_CACHE_H
   2 #define CYGONCE_IMP_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      imp_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   nickg
  47 // Contributors:        nickg, dmoseley
  48 // Date:        1998-02-17
  49 // Purpose:     Cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations.
  52 // Usage:
  53 //              #include <cyg/hal/imp_cache.h>
  54 //              ...
  55 //
  56 //
  57 //####DESCRIPTIONEND####
  58 //
  59 //=============================================================================
  60
  61 #include <pkgconf/hal.h>
  62 #include <cyg/infra/cyg_type.h>
  63
  64 #include <cyg/hal/mips-regs.h>
  65 #include <cyg/hal/hal_arch.h>
  66 #include <cyg/hal/plf_cache.h>
  67 #include <cyg/hal/var_arch.h>
  68
  69 #ifdef CYGHWR_HAL_MIPS_MIPS64_CORE_5K
  70
  71 //-----------------------------------------------------------------------------
  72 // Cache dimensions
  73
  74 // Data cache
  75 #define HAL_DCACHE_SIZE                 8192    // Size of data cache in bytes
  76 #define HAL_DCACHE_LINE_SIZE            32      // Size of a data cache line
  77 #define HAL_DCACHE_WAYS                 2       // Associativity of the cache
  78
  79 // Instruction cache
  80 #define HAL_ICACHE_SIZE                 8192    // Size of cache in bytes
  81 #define HAL_ICACHE_LINE_SIZE            32      // Size of a cache line
  82 #define HAL_ICACHE_WAYS                 2       // Associativity of the cache
  83
  84 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  85 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  86
  87 #define HAL_DCACHE_WRITETHRU_MODE       1
  88 #define HAL_DCACHE_WRITEBACK_MODE       0
  89
  90 #else
  91
  92 #error Unknown MIPS32 Variant
  93
  94 #endif
  95
  96 //-----------------------------------------------------------------------------
  97 // General cache defines.
  98 #define HAL_CLEAR_TAGLO()  asm volatile (" mtc0 $0, $28;" \
  99                                              " nop;"      \
 100                                              " nop;"      \
 101                                              " nop;")
 102 #define HAL_CLEAR_TAGHI()  asm volatile (" mtc0 $0, $29;" \
 103                                              " nop;"      \
 104                                              " nop;"      \
 105                                              " nop;")
 106
 107 /* Cache instruction opcodes */
 108 #define HAL_CACHE_OP(which, op)             (which | (op << 2))
 109
 110 #define HAL_WHICH_ICACHE                    0x0
 111 #define HAL_WHICH_DCACHE                    0x1
 112
 113 #define HAL_INDEX_INVALIDATE                0x0
 114 #define HAL_INDEX_LOAD_TAG                  0x1
 115 #define HAL_INDEX_STORE_TAG                 0x2
 116 #define HAL_HIT_INVALIDATE                  0x4
 117 #define HAL_ICACHE_FILL                     0x5
 118 #define HAL_DCACHE_HIT_INVALIDATE           0x5
 119 #define HAL_DCACHE_HIT_WRITEBACK            0x6
 120 #define HAL_FETCH_AND_LOCK                  0x7
 121
 122 //-----------------------------------------------------------------------------
 123 // Global control of data cache
 124
 125 // Invalidate the entire cache
 126 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
 127 #define HAL_DCACHE_INVALIDATE_ALL()                                                     \
 128     CYG_MACRO_START                                                                     \
 129     register volatile CYG_BYTE *addr;                                                   \
 130     HAL_CLEAR_TAGLO();                                                                  \
 131     HAL_CLEAR_TAGHI();                                                                  \
 132     for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE;                                    \
 133          addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_DCACHE_SIZE);                \
 134          addr += HAL_DCACHE_LINE_SIZE )                                                 \
 135     {                                                                                   \
 136         asm volatile (" cache %0, 0(%1)"                                                \
 137                       :                                                                 \
 138                       : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_INDEX_STORE_TAG)),      \
 139                         "r"(addr));                                                     \
 140     }                                                                                   \
 141     CYG_MACRO_END
 142
 143 // Synchronize the contents of the cache with memory.
 144 extern void hal_dcache_sync(void);
 145 #define HAL_DCACHE_SYNC_DEFINED
 146 #define HAL_DCACHE_SYNC() hal_dcache_sync()
 147
 148 // Set the data cache refill burst size
 149 //#define HAL_DCACHE_BURST_SIZE(_asize_)
 150
 151 // Set the data cache write mode
 152 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 153
 154 // Load the contents of the given address range into the data cache
 155 // and then lock the cache so that it stays there.
 156 #define HAL_DCACHE_LOCK_DEFINED
 157 #define HAL_DCACHE_LOCK(_base_, _asize_)                                                \
 158     CYG_MACRO_START                                                                     \
 159     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 160     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 161     register CYG_WORD _size_ = (_asize_);                                               \
 162     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 163       asm volatile (" cache %0, 0(%1)"                                                  \
 164                     :                                                                   \
 165                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_FETCH_AND_LOCK)),         \
 166                       "r"(_addr_));                                                     \
 167     CYG_MACRO_END
 168
 169 // Undo a previous lock operation
 170 #define HAL_DCACHE_UNLOCK_DEFINED
 171 #define HAL_DCACHE_UNLOCK(_base_, _asize_)                                              \
 172     CYG_MACRO_START                                                                     \
 173     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 174     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 175     register CYG_WORD _size_ = (_asize_);                                               \
 176     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 177       asm volatile (" cache %0, 0(%1)"                                                  \
 178                     :                                                                   \
 179                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
 180                       "r"(_addr_));                                                     \
 181     CYG_MACRO_END
 182
 183 // Unlock entire cache
 184 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
 185 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 186
 187
 188 //-----------------------------------------------------------------------------
 189 // Data cache line control
 190
 191 // Allocate cache lines for the given address range without reading its
 192 // contents from memory.
 193 //#define HAL_DCACHE_ALLOCATE( _base_ , _asize_ )
 194
 195 // Write dirty cache lines to memory and invalidate the cache entries
 196 // for the given address range.
 197 #define HAL_DCACHE_FLUSH_DEFINED
 198 #if HAL_DCACHE_WRITETHRU_MODE == 1
 199 // No need to flush a writethrough cache
 200 #define HAL_DCACHE_FLUSH( _base_ , _asize_ )
 201 #else
 202 #error HAL_DCACHE_FLUSH undefined for MIPS32 writeback cache
 203 #endif
 204
 205 // Write dirty cache lines to memory for the given address range.
 206 #define HAL_DCACHE_STORE_DEFINED
 207 #if HAL_DCACHE_WRITETHRU_MODE == 1
 208 // No need to store a writethrough cache
 209 #define HAL_DCACHE_STORE( _base_ , _asize_ )
 210 #else
 211 #error HAL_DCACHE_STORE undefined for MIPS32 writeback cache
 212 #endif
 213
 214 // Invalidate cache lines in the given range without writing to memory.
 215 #define HAL_DCACHE_INVALIDATE_DEFINED
 216 #define HAL_DCACHE_INVALIDATE( _base_ , _asize_ )                                       \
 217     CYG_MACRO_START                                                                     \
 218     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 219     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 220     register CYG_WORD _size_ = (_asize_);                                               \
 221     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_DCACHE_LINE_SIZE )                   \
 222       asm volatile (" cache %0, 0(%1)"                                                  \
 223                     :                                                                   \
 224                     : "I" (HAL_CACHE_OP(HAL_WHICH_DCACHE, HAL_HIT_INVALIDATE)),         \
 225                       "r"(_addr_));                                                       \
 226     CYG_MACRO_END
 227
 228
 229
 230
 231
 232
 233 //-----------------------------------------------------------------------------
 234 // Global control of Instruction cache
 235
 236 // Invalidate the entire cache
 237 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
 238 #define HAL_ICACHE_INVALIDATE_ALL()                                                     \
 239     CYG_MACRO_START                                                                     \
 240     register volatile CYG_BYTE *addr;                                                   \
 241     HAL_CLEAR_TAGLO();                                                                  \
 242     HAL_CLEAR_TAGHI();                                                                  \
 243     for (addr = (CYG_BYTE *)CYGARC_KSEG_CACHED_BASE;                                    \
 244          addr < (CYG_BYTE *)(CYGARC_KSEG_CACHED_BASE + HAL_ICACHE_SIZE);                \
 245          addr += HAL_ICACHE_LINE_SIZE )                                                 \
 246     {                                                                                   \
 247         asm volatile (" cache %0, 0(%1)"                                                \
 248                       :                                                                 \
 249                       : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_INDEX_STORE_TAG)),      \
 250                         "r"(addr));                                                     \
 251     }                                                                                   \
 252     CYG_MACRO_END
 253
 254 // Synchronize the contents of the cache with memory.
 255 extern void hal_icache_sync(void);
 256 #define HAL_ICACHE_SYNC_DEFINED
 257 #define HAL_ICACHE_SYNC() hal_icache_sync()
 258
 259 // Set the instruction cache refill burst size
 260 //#define HAL_ICACHE_BURST_SIZE(_asize_)
 261
 262 // Load the contents of the given address range into the data cache
 263 // and then lock the cache so that it stays there.
 264 #define HAL_ICACHE_LOCK_DEFINED
 265 #define HAL_ICACHE_LOCK(_base_, _asize_)                                                \
 266     CYG_MACRO_START                                                                     \
 267     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 268     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 269     register CYG_WORD _size_ = (_asize_);                                               \
 270     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 271       asm volatile (" cache %0, 0(%1)"                                                  \
 272                     :                                                                   \
 273                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_FETCH_AND_LOCK)),         \
 274                       "r"(_addr_));                                                     \
 275     CYG_MACRO_END
 276
 277 // Undo a previous lock operation
 278 #define HAL_ICACHE_UNLOCK_DEFINED
 279 #define HAL_ICACHE_UNLOCK(_base_, _asize_)                                              \
 280     CYG_MACRO_START                                                                     \
 281     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 282     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 283     register CYG_WORD _size_ = (_asize_);                                               \
 284     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 285       asm volatile (" cache %0, 0(%1)"                                                  \
 286                     :                                                                   \
 287                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
 288                       "r"(_addr_));                                                     \
 289     CYG_MACRO_END
 290
 291 // Unlock entire cache
 292 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
 293 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0,HAL_ICACHE_SIZE)
 294
 295 //-----------------------------------------------------------------------------
 296 // Instruction cache line control
 297
 298 // Invalidate cache lines in the given range without writing to memory.
 299 #define HAL_ICACHE_INVALIDATE_DEFINED
 300 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                                       \
 301     CYG_MACRO_START                                                                     \
 302     register CYG_ADDRESS _baddr_ = (CYG_ADDRESS)(_base_);                               \
 303     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                                \
 304     register CYG_WORD _size_ = (_asize_);                                               \
 305     for( ; _addr_ <= _baddr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )                   \
 306       asm volatile (" cache %0, 0(%1)"                                                  \
 307                     :                                                                   \
 308                     : "I" (HAL_CACHE_OP(HAL_WHICH_ICACHE, HAL_HIT_INVALIDATE)),         \
 309                       "r"(_addr_));                                                     \
 310     CYG_MACRO_END
 311
 312 //-----------------------------------------------------------------------------
 313 #endif // ifndef CYGONCE_IMP_CACHE_H
 314 // End of imp_cache.h