1 #ifndef CYGONCE_HAL_PLF_INTR_H
2 #define CYGONCE_HAL_PLF_INTR_H
4 //==========================================================================
8 // Ocelot Interrupt and clock support
10 //==========================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
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41 // -------------------------------------------
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43 //==========================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: jskov, nickg
49 // Purpose: Define Interrupt support
50 // Description: The macros defined here provide the HAL APIs for handling
51 // interrupts and the clock for the REF4955 board.
54 // #include <cyg/hal/plf_intr.h>
58 //####DESCRIPTIONEND####
60 //==========================================================================
62 #include <pkgconf/hal.h>
64 #include <cyg/infra/cyg_type.h>
66 //--------------------------------------------------------------------------
69 #ifndef CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
71 // The first 10 correspond to the interrupt lines in the status/cause regs
72 #define CYGNUM_HAL_INTERRUPT_ETH0 0
73 #define CYGNUM_HAL_INTERRUPT_ETH1 1
74 #define CYGNUM_HAL_INTERRUPT_UART1 2
75 #define CYGNUM_HAL_INTERRUPT_21555 3
76 #define CYGNUM_HAL_INTERRUPT_GALILEO 4
77 #define CYGNUM_HAL_INTERRUPT_COMPARE 5
78 #define CYGNUM_HAL_INTERRUPT_PMC1 6
79 #define CYGNUM_HAL_INTERRUPT_PMC2 7
80 #define CYGNUM_HAL_INTERRUPT_CPCI 8
81 #define CYGNUM_HAL_INTERRUPT_UART2 9
83 // PCI interrupts are hardwired for the devices connected to the bus
84 #define CYGNUM_HAL_INTERRUPT_PCI_INTA CYGNUM_HAL_INTERRUPT_GALILEO
85 #define CYGNUM_HAL_INTERRUPT_PCI_INTB CYGNUM_HAL_INTERRUPT_ETH0
86 #define CYGNUM_HAL_INTERRUPT_PCI_INTC CYGNUM_HAL_INTERRUPT_GALILEO
87 #define CYGNUM_HAL_INTERRUPT_PCI_INTD CYGNUM_HAL_INTERRUPT_GALILEO
89 // Min/Max ISR numbers and how many there are
90 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_ETH0
91 #define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_UART2
92 #define CYGNUM_HAL_ISR_COUNT (CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1)
94 // The vector used by the Real time clock
95 #define CYGNUM_HAL_INTERRUPT_RTC CYGNUM_HAL_INTERRUPT_COMPARE
97 #define CYGHWR_HAL_INTERRUPT_VECTORS_DEFINED
101 //--------------------------------------------------------------------------
102 // Interrupt controller information
105 #define CYGARC_REG_INT_STAT 0xb80000ec
107 #define CYGARC_REG_INT_CFG0 0xb80000e0
108 #define CYGARC_REG_INT_CFG1 0xb80000e4
109 #define CYGARC_REG_INT_CFG2 0xb80000e8
110 #define CYGARC_REG_INT_CFG3 0xb8000158
112 #define CYGARC_REG_INT_CFG_INT0 0x00000100
113 #define CYGARC_REG_INT_CFG_INT1 0x00000200
114 #define CYGARC_REG_INT_CFG_INT2 0x00000400
115 #define CYGARC_REG_INT_CFG_INT3 0x00000800
119 #define CYGARC_REG_PCI_STAT 0xb5300000
120 #define CYGARC_REG_PCI_MASK 0xb5300030
122 #define CYGARC_REG_IO_STAT 0xb5300010
123 #define CYGARC_REG_IO_MASK 0xb5300040
126 //----------------------------------------------------------------------------
128 // Uses Secondary Reset Bit in 21555. Don't know where it is mapped though.
129 #define CYGARC_REG_BOARD_RESET 0x????????
131 #define HAL_PLATFORM_RESET() /* HAL_WRITE_UINT8(CYGARC_REG_BOARD_RESET,1) */
133 #define HAL_PLATFORM_RESET_ENTRY 0xbfc00000
135 //--------------------------------------------------------------------------
136 #endif // ifndef CYGONCE_HAL_PLF_INTR_H