packages/hal/mips/tx39/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_IMP_CACHE_H
   2 #define CYGONCE_IMP_CACHE_H
   3
   4 //=============================================================================
   5 //
   6 //      imp_cache.h
   7 //
   8 //      HAL cache control API
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   nickg
  47 // Contributors:        nickg
  48 // Date:        1998-02-17
  49 // Purpose:     Cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations.
  52 // Usage:
  53 //              #include <cyg/hal/imp_cache.h>
  54 //              ...
  55 //
  56 //
  57 //####DESCRIPTIONEND####
  58 //
  59 //=============================================================================
  60
  61 #include <pkgconf/hal.h>
  62 #include <cyg/infra/cyg_type.h>
  63
  64 #include <cyg/hal/plf_cache.h>
  65
  66 //=============================================================================
  67 // Toshiba TX3904
  68
  69 #ifdef CYGPKG_HAL_MIPS_TX3904
  70
  71 //-----------------------------------------------------------------------------
  72 // Cache dimensions
  73
  74 // Data cache
  75 #define HAL_DCACHE_SIZE                 1024    // Size of data cache in bytes
  76 #define HAL_DCACHE_LINE_SIZE            4       // Size of a data cache line
  77 #define HAL_DCACHE_WAYS                 2       // Associativity of the cache
  78
  79 // Instruction cache
  80 #define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
  81 #define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
  82 #define HAL_ICACHE_WAYS                 1       // Associativity of the cache
  83
  84 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
  85 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
  86
  87 //-----------------------------------------------------------------------------
  88 // Global control of data cache
  89
  90 // Enable the data cache
  91 // This uses a bit in the config register, which is TX39 specific.
  92 #define HAL_DCACHE_ENABLE_DEFINED
  93 #define HAL_DCACHE_ENABLE()                     \
  94 {                                               \
  95     asm volatile ("mfc0 $2,$3;"                 \
  96                   "ori  $2,$2,0x0010;"          \
  97                   "mtc0 $2,$3;"                 \
  98                   :                             \
  99                   :                             \
 100                   : "$2"                        \
 101                  );                             \
 102                                                 \
 103 }
 104
 105 // Disable the data cache
 106 #define HAL_DCACHE_DISABLE_DEFINED
 107 #define HAL_DCACHE_DISABLE()                    \
 108 {                                               \
 109     asm volatile ("mfc0 $2,$3;"                 \
 110                   "la   $3,0xFFFFFFEF;"         \
 111                   "and  $2,$2,$3;"              \
 112                   "mtc0 $2,$3;"                 \
 113                   :                             \
 114                   :                             \
 115                   : "$2", "$3"                  \
 116                  );                             \
 117                                                 \
 118 }
 119
 120
 121 // Invalidate the entire cache
 122 // The TX39 only has hit-invalidate on the DCACHE, not
 123 // index-invalidate, so we cannot just empty the cache out without
 124 // knowing what is in it. This is annoying. So, the best we can do is
 125 // fill the cache with data that is unlikely to be there
 126 // otherwise. Hence we read bytes from the ROM space since this is
 127 // most likely to be code, and will not get out of sync even if it is not.
 128 #define HAL_DCACHE_INVALIDATE_ALL_DEFINED
 129 #define HAL_DCACHE_INVALIDATE_ALL()                                     \
 130 {                                                                       \
 131     volatile CYG_BYTE *addr = (CYG_BYTE *)(0x9fc00000);                 \
 132     volatile CYG_BYTE tmp = 0;                                          \
 133     int i;                                                              \
 134     for( i = 0; i < (HAL_DCACHE_SIZE*2); i += HAL_DCACHE_LINE_SIZE )    \
 135     {                                                                   \
 136         tmp = addr[i];                                                  \
 137     }                                                                   \
 138 }
 139
 140 // Synchronize the contents of the cache with memory.
 141 #define HAL_DCACHE_SYNC_DEFINED
 142 #define HAL_DCACHE_SYNC() HAL_DCACHE_INVALIDATE_ALL()
 143
 144 // Set the data cache refill burst size
 145 //#define HAL_DCACHE_BURST_SIZE(_size_)
 146
 147 // Set the data cache write mode
 148 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
 149
 150 //#define HAL_DCACHE_WRITETHRU_MODE       0
 151 //#define HAL_DCACHE_WRITEBACK_MODE       1
 152
 153 // Load the contents of the given address range into the data cache
 154 // and then lock the cache so that it stays there.
 155 #define HAL_DCACHE_LOCK_DEFINED
 156 #define HAL_DCACHE_LOCK(_base_, _size_)         \
 157 {                                               \
 158     asm volatile ("mfc0 $2,$7;"                 \
 159                   "ori  $2,$2,0x0100;"          \
 160                   "mtc0 $2,$7;"                 \
 161                   :                             \
 162                   :                             \
 163                   : "$2"                        \
 164                  );                             \
 165 }
 166
 167 // Undo a previous lock operation
 168 #define HAL_DCACHE_UNLOCK_DEFINED
 169 #define HAL_DCACHE_UNLOCK(_base_, _size_)       \
 170 {                                               \
 171     asm volatile ("mfc0 $2,$7;"                 \
 172                   "la   $3,0xFFFFFEFF;"         \
 173                   "and  $2,$2,$3;"              \
 174                   "mtc0 $2,$7;"                 \
 175                   :                             \
 176                   :                             \
 177                   : "$2", "$3"                  \
 178                  );                             \
 179 }
 180
 181 // Unlock entire cache
 182 #define HAL_DCACHE_UNLOCK_ALL_DEFINED
 183 #define HAL_DCACHE_UNLOCK_ALL() HAL_DCACHE_UNLOCK(0,HAL_DCACHE_SIZE)
 184
 185
 186 //-----------------------------------------------------------------------------
 187 // Data cache line control
 188
 189 // Allocate cache lines for the given address range without reading its
 190 // contents from memory.
 191 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 192
 193 // Write dirty cache lines to memory and invalidate the cache entries
 194 // for the given address range.
 195 //#define HAL_DCACHE_FLUSH( _base_ , _size_ )
 196 #define HAL_DCACHE_FLUSH_DEFINED        // Ensure no default definition
 197
 198 // Write dirty cache lines to memory for the given address range.
 199 //#define HAL_DCACHE_STORE( _base_ , _size_ )
 200 #define HAL_DCACHE_STORE_DEFINED        // Disable default definition
 201
 202 //-----------------------------------------------------------------------------
 203 // Global control of Instruction cache
 204
 205 // Enable the instruction cache
 206 // This uses a bit in the config register, which is TX39 specific.
 207 #define HAL_ICACHE_ENABLE_DEFINED
 208 #define HAL_ICACHE_ENABLE()                     \
 209 {                                               \
 210     asm volatile ("mfc0 $2,$3;"                 \
 211                   "ori  $2,$2,0x0020;"          \
 212                   "mtc0 $2,$3;"                 \
 213                   :                             \
 214                   :                             \
 215                   : "$2"                        \
 216                  );                             \
 217                                                 \
 218 }
 219
 220 // Disable the instruction cache
 221 #define HAL_ICACHE_DISABLE_DEFINED
 222 #define HAL_ICACHE_DISABLE()                    \
 223 {                                               \
 224     asm volatile ("mfc0 $2,$3;"                 \
 225                   "la   $3,0xFFFFFFDF;"         \
 226                   "and  $2,$2,$3;"              \
 227                   "mtc0 $2,$3;"                 \
 228                   "j    1f;"                    \
 229                   "nop;"                        \
 230                   ".balign 16,0;"               \
 231                   "1:;"                         \
 232                   :                             \
 233                   :                             \
 234                   : "$2", "$3"                  \
 235                  );                             \
 236                                                 \
 237 }
 238
 239 // Load the contents of the given address range into the instruction cache
 240 // and then lock the cache so that it stays there.
 241 #define HAL_ICACHE_LOCK_DEFINED
 242 #define HAL_ICACHE_LOCK(_base_, _size_)         \
 243 {                                               \
 244     asm volatile ("mfc0 $2,$7;"                 \
 245                   "ori  $2,$2,0x0200;"          \
 246                   "mtc0 $2,$7;"                 \
 247                   :                             \
 248                   :                             \
 249                   : "$2"                        \
 250                  );                             \
 251 }
 252
 253 // Undo a previous lock operation
 254 #define HAL_ICACHE_UNLOCK_DEFINED
 255 #define HAL_ICACHE_UNLOCK(_base_, _size_)       \
 256 {                                               \
 257     asm volatile ("mfc0 $2,$7;"                 \
 258                   "la   $3,0xFFFFFDFF;"         \
 259                   "and  $2,$2,$3;"              \
 260                   "mtc0 $2,$7;"                 \
 261                   :                             \
 262                   :                             \
 263                   : "$2", "$3"                  \
 264                  );                             \
 265 }
 266
 267 // Unlock entire cache
 268 #define HAL_ICACHE_UNLOCK_ALL_DEFINED
 269 #define HAL_ICACHE_UNLOCK_ALL() HAL_ICACHE_UNLOCK(0, HAL_ICACHE_SIZE)
 270
 271 //-----------------------------------------------------------------------------
 272 // Instruction cache line control
 273 // On the TX39, the instruction cache must be disabled to use the index-invalidate
 274 // cache operation.
 275
 276 // Invalidate the entire cache
 277 // This uses the index-invalidate cache operation.
 278 #define HAL_ICACHE_INVALIDATE_ALL_DEFINED
 279 #define HAL_ICACHE_INVALIDATE_ALL()                                             \
 280 {                                                                               \
 281     register CYG_ADDRESS _baddr_ = 0x80000000;                                  \
 282     register CYG_ADDRESS _addr_ = 0x80000000;                                   \
 283     register CYG_WORD _state_;                                                  \
 284     HAL_ICACHE_IS_ENABLED(_state_);                                             \
 285     HAL_ICACHE_DISABLE();                                                       \
 286     for( ; _addr_ < _baddr_+HAL_ICACHE_SIZE; _addr_ += HAL_ICACHE_LINE_SIZE )   \
 287     {                                                                           \
 288         asm volatile ("cache 0x00,0(%0)" : : "r"(_addr_) );                     \
 289     }                                                                           \
 290     if( _state_ ) HAL_ICACHE_ENABLE();                                          \
 291 }
 292
 293 // Invalidate cache lines in the given range without writing to memory.
 294 // This uses the index-invalidate cache operation since the TX39 does not
 295 // have hit-invalidate on the instruction cache.
 296 #define HAL_ICACHE_INVALIDATE_DEFINED
 297 #define HAL_ICACHE_INVALIDATE( _base_ , _asize_ )                       \
 298 {                                                                       \
 299     register CYG_ADDRESS _addr_ = (CYG_ADDRESS)(_base_);                \
 300     register CYG_WORD _size_ = (_asize_);                               \
 301     register CYG_WORD _state_;                                          \
 302     HAL_ICACHE_IS_ENABLED(_state_);                                     \
 303     HAL_ICACHE_DISABLE();                                               \
 304     for( ; _addr_ <= _addr_+_size_; _addr_ += HAL_ICACHE_LINE_SIZE )    \
 305     {                                                                   \
 306         asm volatile ("cache 0,0(%0)" : : "r"(_addr_) );                \
 307     }                                                                   \
 308     if( _state_ ) HAL_ICACHE_ENABLE();                                  \
 309 }
 310
 311 #endif // CYGPKG_HAL_MIPS_TX3904
 312
 313 //-----------------------------------------------------------------------------
 314 #endif // ifndef CYGONCE_IMP_CACHE_H
 315 // End of imp_cache.h