1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
7 ## AM31 assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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28 ## As a special exception, if other files instantiate templates or use macros
29 ## or inline functions from this file, or you compile this file and link it
30 ## with other works to produce a work based on this file, this file does not
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32 ## License. However the source code for this file must still be made available
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40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
46 ## Contributors: nickg
48 ## Purpose: AM31 definitions.
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the AM31 CPU variant.
52 ## #include <cyg/hal/variant.inc>
56 ######DESCRIPTIONEND####
58 ##=============================================================================
60 #include <pkgconf/hal.h>
62 #include <cyg/hal/platform.inc>
65 #------------------------------------------------------------------------------
66 # Register definitions
68 #define NMICR 0x34000100 // NMI control register
69 #define DCR 0x20000030 // Debug control register
70 #define ISR 0x20000034 // Interrupt control register
72 #define DCR_DE 0x0010 // DE bit in DCR
74 #------------------------------------------------------------------------------
75 # CPU state save and restore macros
77 .macro hal_cpu_save_all
78 movm [d2,d3,a2,a3,other],(sp) # push all registers
81 .macro hal_cpu_load_all
82 movm (sp),[d2,d3,a2,a3,other] # pop regs
85 .macro hal_cpu_get_psw reg
89 .macro hal_cpu_set_psw reg
93 # Location of PC in saved register context (HAL_SavedRegisters)
94 #define SAVED_CONTEXT_PC_OFFSET 56
96 ##-----------------------------------------------------------------------------
97 # It appears that there is an undocumented extra bit
98 # in the PSW that masks the delivery of NMIs. It is in
99 # the upper 16 bits of the register that we cannot access
100 # directly. So, to clear it, we must set up a fake interrupt
101 # state and do an RTI to load the PSW. We need to do this if
102 # we are going to be able to set breakpoints in NMI handlers.
103 # Note that the AM33 has a documented NMID at bit 17 of the
104 # extended PSW (along with instructions to access it).
106 .macro hal_cpu_clear_nmid
107 mov PSW,d3 # D3 = PSW
109 mov nmid\@,d2 # D2 = Next PC
110 movm [d2,d3],(sp) # Push
111 rti # and load into CPU
116 ##-----------------------------------------------------------------------------
117 ## Register addresses and initialization values
119 .equ IOBCTR ,0x32000010
120 .equ MEMCTR0 ,0x32000020
121 .equ MEMCTR1 ,0x32000022
122 .equ MEMCTR2 ,0x32000024
123 .equ MEMCTR3 ,0x32000026
124 .equ MEMCTR4 ,0x32000028
125 .equ MEMCTR5 ,0x3200002a
126 .equ MEMCTR6 ,0x3200002c
127 .equ MEMCTR7 ,0x3200002e
128 .equ DRAMCTR ,0x32000040
129 .equ REFCNT ,0x32000042
131 .equ INIT_MEMCTR0,0x1200 # 2wait
132 .equ INIT_MEMCTR1,0x0120 # 1wait-32bit-
133 .equ INIT_MEMCTR2,0x0065
134 .equ INIT_DRAMCTR,0x0287
135 .equ INIT_REFCNT,0x00eb
137 .equ P2OUT ,0x36008004
138 .equ P2MD ,0x36008024
139 .equ P2SS ,0x36008044
140 .equ P2DIR ,0x36008064
145 #------------------------------------------------------------------------------
148 #ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
167 #define CYGPKG_HAL_MN10300_MEMC_DEFINED
171 ##-----------------------------------------------------------------------------
172 # Default interrupt decoding macros.
174 #ifndef CYGPKG_HAL_MN10300_INTC_DEFINED
178 # initialize all interrupts to disabled
182 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
184 #define CYG_ISR_TABLE_SIZE 10
186 .macro hal_intc_decode dreg,areg,dreg1
187 mov _mn10300_interrupt_control,\areg
188 movhu (0x100,\areg),\dreg1 # dreg1 = IAGR
189 mov (0,a2),\dreg # dreg = vector priority
190 mov \dreg1,(0,a2) # store real vector in saved state
191 asl 2,\dreg # dreg = byte index of isr
192 add 12,\dreg # skip NMI vectors
195 #define CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED
199 #define CYG_ISR_TABLE_SIZE 34
201 # decode the interrupt
202 .macro hal_intc_decode dreg,areg,dreg1
203 mov _mn10300_interrupt_control,\areg
204 movhu (0x100,\areg),\dreg # dreg = IAGR
205 mov \dreg,(0,a2) # store real vector in saved state
206 add 12,\dreg # skip NMI vectors
209 #define CYGPKG_HAL_MN10300_INTC_DECODE_DEFINED
213 #define CYGPKG_HAL_MN10300_INTC_DEFINED
218 #------------------------------------------------------------------------------
219 # Diagnostics macros.
221 #ifndef CYGPKG_HAL_MN10300_DIAG_DEFINED
231 .macro hal_diag_excpt_start
234 .macro hal_diag_intr_start
237 .macro hal_diag_restore
240 .macro hal_diag_led val
251 led_value: .byte 0x40
252 led_foo1: .byte 0x00 # Keep alignment to work around compiler/linker bug
257 #define CYGPKG_HAL_MN10300_DIAG_DEFINED
261 #------------------------------------------------------------------------------
262 # Monitor initialization.
264 #ifndef CYGPKG_HAL_MN10300_MON_DEFINED
271 #if defined(CYG_HAL_STARTUP_ROM) || \
272 defined(CYGPKG_HAL_MN10300_AM31_SIM)
273 .macro hal_mon_init_vectors
274 mov _mn10300_interrupt_vectors,a0
275 mov __hardware_vector_0,d0
277 mov __hardware_vector_1,d0
279 mov __hardware_vector_2,d0
281 mov __hardware_vector_3,d0
283 mov __hardware_vector_4,d0
285 mov __hardware_vector_5,d0
287 mov __hardware_vector_6,d0
291 .macro hal_mon_init_vectors
295 #if defined(CYG_HAL_STARTUP_RAM)
297 # init vsr table in SRAM where the ROM
298 # vectors the interrupts.
300 .macro hal_mon_init_vsr
301 mov _hal_vsr_table,a0
302 mov __default_interrupt_vsr,d0
306 #ifndef CYGSEM_HAL_USE_ROM_MONITOR_CygMon
307 # When using Cygmon, leave level 3 for GDB
314 mov __default_nmi_vsr,d0
316 mov __default_trap_vsr,d0
321 .macro hal_mon_init_vsr
325 #if !(defined(CYG_HAL_STARTUP_ROM) || \
326 defined(CYGPKG_HAL_MN10300_AM31_SIM) || \
327 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
329 #define CYG_HAL_MN10300_VSR_TABLE_DEFINED
335 #define CYGPKG_HAL_MN10300_MON_DEFINED
341 #------------------------------------------------------------------------------
342 #endif // ifndef CYGONCE_HAL_VARIANT_INC