packages/hal/mn10300/am33/v2_0/include/var_intr.h

   1 #ifndef CYGONCE_HAL_VAR_INTR_H
   2 #define CYGONCE_HAL_VAR_INTR_H
   3
   4 //==========================================================================
   5 //
   6 //      var_intr.h
   7 //
   8 //      AM33 Interrupt and clock support
   9 //
  10 //==========================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //==========================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    nickg
  47 // Contributors: nickg, jskov,
  48 //               gthomas, jlarmour, dmoseley
  49 // Date:         1999-02-16
  50 // Purpose:      VR4300 Interrupt support
  51 // Description:  The macros defined here provide the HAL APIs for handling
  52 //               interrupts and the clock for AM33 variants of the MN10300
  53 //               architecture.
  54 //
  55 // Usage:
  56 //              #include <cyg/hal/var_intr.h>
  57 //              ...
  58 //
  59 //
  60 //####DESCRIPTIONEND####
  61 //
  62 //==========================================================================
  63
  64 #include <pkgconf/hal.h>
  65
  66 #include <cyg/infra/cyg_type.h>
  67
  68 #include <cyg/hal/plf_intr.h>
  69
  70 //--------------------------------------------------------------------------
  71
  72 // The MN10300 has a somewhat complex interrupt structure. Besides the
  73 // reset and NMI vectors there are seven maskable interrupt vectors
  74 // which must point to code in the 64k starting at 0x40000000. There
  75 // are also 25 Interrupt control groups, each of which can have 4
  76 // interrupt lines attached, for a theoretical total of 100 interrupts
  77 // (!). Some of these are dedicated to specific devices, other to
  78 // external pins, and others are not connected to anything, resulting
  79 // in only 45 that can actually be delivered. Each control group may
  80 // be assigned one of seven interrupt levels, and is delivered to the
  81 // corresponding vector. Software can then use a register to determine
  82 // the delivering group and detect from there which interrupt has been
  83 // delivered.
  84 //
  85 // The approach we will adopt at present is for the code attached to
  86 // each vector to save state and jump via a table to a VSR. The
  87 // default VSR will fully decode the delivered interrupt into a table
  88 // of isr/data/object entries. VSR replacement will operate on the
  89 // first level indirection table rather than the hardware
  90 // vectors. This is the fastest mechanism, however it needs 100*3*4 +
  91 // 7*4 = 1228 bytes for the tables.
  92 //
  93
  94 //--------------------------------------------------------------------------
  95 // Interrupt vectors.
  96
  97 // The level-specific hardware vectors
  98 // These correspond to VSRs and are the values to use for HAL_VSR_GET/SET
  99 #define CYGNUM_HAL_VECTOR_0                     0
 100 #define CYGNUM_HAL_VECTOR_1                     1
 101 #define CYGNUM_HAL_VECTOR_2                     2
 102 #define CYGNUM_HAL_VECTOR_3                     3
 103 #define CYGNUM_HAL_VECTOR_4                     4
 104 #define CYGNUM_HAL_VECTOR_5                     5
 105 #define CYGNUM_HAL_VECTOR_6                     6
 106 #define CYGNUM_HAL_VECTOR_NMI_ENTRY             7
 107 #define CYGNUM_HAL_VECTOR_TRAP                  8
 108 #define CYGNUM_HAL_VECTOR_NMI                   9
 109 #define CYGNUM_HAL_VECTOR_WATCHDOG              10
 110 #define CYGNUM_HAL_VECTOR_SYSTEM_ERROR          11
 111 #define CYGNUM_HAL_VECTOR_JTAG                  12
 112 #define CYGNUM_HAL_VECTOR_ISTEP                 13
 113 #define CYGNUM_HAL_VECTOR_MISSA                 14
 114 #define CYGNUM_HAL_VECTOR_UNIMP                 15
 115 #define CYGNUM_HAL_VECTOR_PIEXE                 16
 116 #define CYGNUM_HAL_VECTOR_MEMERR                17
 117 #define CYGNUM_HAL_VECTOR_IBREAK                18
 118 #define CYGNUM_HAL_VECTOR_DBSRL                 19
 119 #define CYGNUM_HAL_VECTOR_PERIDB                20
 120 #define CYGNUM_HAL_VECTOR_EXUNIMP               21
 121 #define CYGNUM_HAL_VECTOR_OBREAK                22
 122 #define CYGNUM_HAL_VECTOR_PRIV                  23
 123 #define CYGNUM_HAL_VECTOR_BUSERR                24
 124 #define CYGNUM_HAL_VECTOR_DBFLT                 25
 125 #define CYGNUM_HAL_VECTOR_UNUSED_1              26
 126 #define CYGNUM_HAL_VECTOR_UNUSED_2              27
 127
 128
 129 #define CYGNUM_HAL_VSR_MIN                      0
 130 #define CYGNUM_HAL_VSR_MAX                      27
 131 #define CYGNUM_HAL_VSR_COUNT                    28
 132
 133 // Exception numbers. These are the values used when passed out to an
 134 // external exception handler using cyg_hal_deliver_exception()
 135
 136 #define CYGNUM_HAL_EXCEPTION_NMI               CYGNUM_HAL_VECTOR_NMI
 137 #define CYGNUM_HAL_EXCEPTION_WATCHDOG          CYGNUM_HAL_VECTOR_WATCHDOG
 138 #define CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR      CYGNUM_HAL_VECTOR_SYSTEM_ERROR
 139 #define CYGNUM_HAL_EXCEPTION_TRAP              CYGNUM_HAL_VECTOR_TRAP
 140 #define CYGNUM_HAL_EXCEPTION_JTAG              CYGNUM_HAL_VECTOR_JTAG
 141 #define CYGNUM_HAL_EXCEPTION_ISTEP             CYGNUM_HAL_VECTOR_ISTEP
 142 #define CYGNUM_HAL_EXCEPTION_MISSA             CYGNUM_HAL_VECTOR_MISSA
 143 #define CYGNUM_HAL_EXCEPTION_UNIMP             CYGNUM_HAL_VECTOR_UNIMP
 144 #define CYGNUM_HAL_EXCEPTION_PIEXE             CYGNUM_HAL_VECTOR_PIEXE
 145 #define CYGNUM_HAL_EXCEPTION_MEMERR            CYGNUM_HAL_VECTOR_MEMERR
 146 #define CYGNUM_HAL_EXCEPTION_IBREAK            CYGNUM_HAL_VECTOR_IBREAK
 147 #define CYGNUM_HAL_EXCEPTION_DBSRL             CYGNUM_HAL_VECTOR_DBSRL
 148 #define CYGNUM_HAL_EXCEPTION_PERIDB            CYGNUM_HAL_VECTOR_PERIDB
 149 #define CYGNUM_HAL_EXCEPTION_EXUNIMP           CYGNUM_HAL_VECTOR_EXUNIMP
 150 #define CYGNUM_HAL_EXCEPTION_OBREAK            CYGNUM_HAL_VECTOR_OBREAK
 151 #define CYGNUM_HAL_EXCEPTION_PRIV              CYGNUM_HAL_VECTOR_PRIV
 152 #define CYGNUM_HAL_EXCEPTION_BUSERR            CYGNUM_HAL_VECTOR_BUSERR
 153 #define CYGNUM_HAL_EXCEPTION_DBLFLT            CYGNUM_HAL_VECTOR_DBLFLT
 154
 155
 156 #define CYGNUM_HAL_EXCEPTION_MIN               CYGNUM_HAL_VSR_MIN
 157 #define CYGNUM_HAL_EXCEPTION_MAX               CYGNUM_HAL_VSR_MAX
 158 #define CYGNUM_HAL_EXCEPTION_COUNT             CYGNUM_HAL_VSR_COUNT
 159
 160 #define CYGNUM_HAL_EXCEPTION_INTERRUPT         CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR
 161 #define CYGNUM_HAL_VECTOR_BREAKPOINT           CYGNUM_HAL_EXCEPTION_SYSTEM_ERROR
 162
 163 // Canonical names for various exceptions. These are used
 164 // by generic exception handling code to make sense of
 165 // excptions that have been delivered.
 166
 167 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS       \
 168           CYGNUM_HAL_EXCEPTION_BUSERR
 169 #define CYGNUM_HAL_EXCEPTION_DATA_UNALIGNED_ACCESS \
 170           CYGNUM_HAL_EXCEPTION_MISSA
 171 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION \
 172           CYGNUM_HAL_EXCEPTION_UNIMP
 173
 174
 175 // The decoded interrupts
 176
 177 #define CYGNUM_HAL_INTERRUPT_NMIRQ                0
 178 #define CYGNUM_HAL_INTERRUPT_WATCHDOG             1
 179 #define CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR         2
 180 #define CYGNUM_HAL_INTERRUPT_RESERVED_3           3
 181
 182 #define CYGNUM_HAL_INTERRUPT_RESERVED_4           4
 183 #define CYGNUM_HAL_INTERRUPT_RESERVED_5           5
 184 #define CYGNUM_HAL_INTERRUPT_RESERVED_6           6
 185 #define CYGNUM_HAL_INTERRUPT_RESERVED_7           7
 186
 187 #define CYGNUM_HAL_INTERRUPT_TIMER_0              8
 188 #define CYGNUM_HAL_INTERRUPT_RESERVED_9           9
 189 #define CYGNUM_HAL_INTERRUPT_RESERVED_10          10
 190 #define CYGNUM_HAL_INTERRUPT_RESERVED_11          11
 191
 192 #define CYGNUM_HAL_INTERRUPT_TIMER_1              12
 193 #define CYGNUM_HAL_INTERRUPT_RESERVED_13          13
 194 #define CYGNUM_HAL_INTERRUPT_RESERVED_14          14
 195 #define CYGNUM_HAL_INTERRUPT_RESERVED_15          15
 196
 197 #define CYGNUM_HAL_INTERRUPT_TIMER_2              16
 198 #define CYGNUM_HAL_INTERRUPT_RESERVED_17          17
 199 #define CYGNUM_HAL_INTERRUPT_RESERVED_18          18
 200 #define CYGNUM_HAL_INTERRUPT_RESERVED_19          19
 201
 202 #define CYGNUM_HAL_INTERRUPT_TIMER_3              20
 203 #define CYGNUM_HAL_INTERRUPT_RESERVED_21          21
 204 #define CYGNUM_HAL_INTERRUPT_RESERVED_22          22
 205 #define CYGNUM_HAL_INTERRUPT_RESERVED_23          23
 206
 207 #define CYGNUM_HAL_INTERRUPT_TIMER_4              24
 208 #define CYGNUM_HAL_INTERRUPT_RESERVED_25          25
 209 #define CYGNUM_HAL_INTERRUPT_RESERVED_26          26
 210 #define CYGNUM_HAL_INTERRUPT_RESERVED_27          27
 211
 212 #define CYGNUM_HAL_INTERRUPT_TIMER_5              28
 213 #define CYGNUM_HAL_INTERRUPT_RESERVED_29          29
 214 #define CYGNUM_HAL_INTERRUPT_RESERVED_30          30
 215 #define CYGNUM_HAL_INTERRUPT_RESERVED_31          31
 216
 217 #define CYGNUM_HAL_INTERRUPT_TIMER_6              32
 218 #define CYGNUM_HAL_INTERRUPT_RESERVED_33          33
 219 #define CYGNUM_HAL_INTERRUPT_RESERVED_34          34
 220 #define CYGNUM_HAL_INTERRUPT_RESERVED_35          35
 221
 222 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_A    36
 223 #define CYGNUM_HAL_INTERRUPT_RESERVED_37          37
 224 #define CYGNUM_HAL_INTERRUPT_RESERVED_38          38
 225 #define CYGNUM_HAL_INTERRUPT_RESERVED_39          39
 226
 227 #define CYGNUM_HAL_INTERRUPT_TIMER_6_COMPARE_B    40
 228 #define CYGNUM_HAL_INTERRUPT_RESERVED_41          41
 229 #define CYGNUM_HAL_INTERRUPT_RESERVED_42          42
 230 #define CYGNUM_HAL_INTERRUPT_RESERVED_43          43
 231
 232 #define CYGNUM_HAL_INTERRUPT_TIMER_7              44
 233 #define CYGNUM_HAL_INTERRUPT_RESERVED_45          45
 234 #define CYGNUM_HAL_INTERRUPT_RESERVED_46          46
 235 #define CYGNUM_HAL_INTERRUPT_RESERVED_47          47
 236
 237 #define CYGNUM_HAL_INTERRUPT_TIMER_8              48
 238 #define CYGNUM_HAL_INTERRUPT_RESERVED_49          49
 239 #define CYGNUM_HAL_INTERRUPT_RESERVED_50          50
 240 #define CYGNUM_HAL_INTERRUPT_RESERVED_51          51
 241
 242 #define CYGNUM_HAL_INTERRUPT_TIMER_9              52
 243 #define CYGNUM_HAL_INTERRUPT_RESERVED_53          53
 244 #define CYGNUM_HAL_INTERRUPT_RESERVED_54          54
 245 #define CYGNUM_HAL_INTERRUPT_RESERVED_55          55
 246
 247 #define CYGNUM_HAL_INTERRUPT_TIMER_10             56
 248 #define CYGNUM_HAL_INTERRUPT_RESERVED_57          57
 249 #define CYGNUM_HAL_INTERRUPT_RESERVED_58          58
 250 #define CYGNUM_HAL_INTERRUPT_RESERVED_59          59
 251
 252 #define CYGNUM_HAL_INTERRUPT_TIMER_11             60
 253 #define CYGNUM_HAL_INTERRUPT_RESERVED_61          61
 254 #define CYGNUM_HAL_INTERRUPT_RESERVED_62          62
 255 #define CYGNUM_HAL_INTERRUPT_RESERVED_63          63
 256
 257 #define CYGNUM_HAL_INTERRUPT_DMA0                 64
 258 #define CYGNUM_HAL_INTERRUPT_RESERVED_65          65
 259 #define CYGNUM_HAL_INTERRUPT_RESERVED_66          66
 260 #define CYGNUM_HAL_INTERRUPT_RESERVED_67          67
 261
 262 #define CYGNUM_HAL_INTERRUPT_DMA1                 68
 263 #define CYGNUM_HAL_INTERRUPT_RESERVED_69          69
 264 #define CYGNUM_HAL_INTERRUPT_RESERVED_70          70
 265 #define CYGNUM_HAL_INTERRUPT_RESERVED_71          71
 266
 267 #define CYGNUM_HAL_INTERRUPT_DMA2                 72
 268 #define CYGNUM_HAL_INTERRUPT_RESERVED_73          73
 269 #define CYGNUM_HAL_INTERRUPT_RESERVED_74          74
 270 #define CYGNUM_HAL_INTERRUPT_RESERVED_75          75
 271
 272 #define CYGNUM_HAL_INTERRUPT_DMA3                 76
 273 #define CYGNUM_HAL_INTERRUPT_RESERVED_77          77
 274 #define CYGNUM_HAL_INTERRUPT_RESERVED_78          78
 275 #define CYGNUM_HAL_INTERRUPT_RESERVED_79          79
 276
 277 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_RX          80
 278 #define CYGNUM_HAL_INTERRUPT_RESERVED_81          81
 279 #define CYGNUM_HAL_INTERRUPT_RESERVED_82          82
 280 #define CYGNUM_HAL_INTERRUPT_RESERVED_83          83
 281
 282 #define CYGNUM_HAL_INTERRUPT_SERIAL_0_TX          84
 283 #define CYGNUM_HAL_INTERRUPT_RESERVED_85          85
 284 #define CYGNUM_HAL_INTERRUPT_RESERVED_86          86
 285 #define CYGNUM_HAL_INTERRUPT_RESERVED_87          87
 286
 287 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_RX          88
 288 #define CYGNUM_HAL_INTERRUPT_RESERVED_89          89
 289 #define CYGNUM_HAL_INTERRUPT_RESERVED_90          90
 290 #define CYGNUM_HAL_INTERRUPT_RESERVED_91          91
 291
 292 #define CYGNUM_HAL_INTERRUPT_SERIAL_1_TX          92
 293 #define CYGNUM_HAL_INTERRUPT_RESERVED_93          93
 294 #define CYGNUM_HAL_INTERRUPT_RESERVED_94          94
 295 #define CYGNUM_HAL_INTERRUPT_RESERVED_95          95
 296
 297 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_RX          96
 298 #define CYGNUM_HAL_INTERRUPT_RESERVED_97          97
 299 #define CYGNUM_HAL_INTERRUPT_RESERVED_98          98
 300 #define CYGNUM_HAL_INTERRUPT_RESERVED_99          99
 301
 302 #define CYGNUM_HAL_INTERRUPT_SERIAL_2_TX          100
 303 #define CYGNUM_HAL_INTERRUPT_RESERVED_101         101
 304 #define CYGNUM_HAL_INTERRUPT_RESERVED_102         102
 305 #define CYGNUM_HAL_INTERRUPT_RESERVED_103         103
 306
 307 #define CYGNUM_HAL_INTERRUPT_RESERVED_104         104
 308 #define CYGNUM_HAL_INTERRUPT_RESERVED_105         105
 309 #define CYGNUM_HAL_INTERRUPT_RESERVED_106         106
 310 #define CYGNUM_HAL_INTERRUPT_RESERVED_107         107
 311
 312 #define CYGNUM_HAL_INTERRUPT_TD                   108
 313 #define CYGNUM_HAL_INTERRUPT_RESERVED_109         109
 314 #define CYGNUM_HAL_INTERRUPT_RESERVED_110         110
 315 #define CYGNUM_HAL_INTERRUPT_RESERVED_111         111
 316
 317 #define CYGNUM_HAL_INTERRUPT_AV                   112
 318 #define CYGNUM_HAL_INTERRUPT_RESERVED_113         113
 319 #define CYGNUM_HAL_INTERRUPT_RESERVED_114         114
 320 #define CYGNUM_HAL_INTERRUPT_RESERVED_115         115
 321
 322 #define CYGNUM_HAL_INTERRUPT_TD_DMA               116
 323 #define CYGNUM_HAL_INTERRUPT_RESERVED_117         117
 324 #define CYGNUM_HAL_INTERRUPT_RESERVED_118         118
 325 #define CYGNUM_HAL_INTERRUPT_RESERVED_119         119
 326
 327 #define CYGNUM_HAL_INTERRUPT_IC_IF_0              120
 328 #define CYGNUM_HAL_INTERRUPT_RESERVED_121         121
 329 #define CYGNUM_HAL_INTERRUPT_RESERVED_122         122
 330 #define CYGNUM_HAL_INTERRUPT_RESERVED_123         123
 331
 332 #define CYGNUM_HAL_INTERRUPT_IC_IF_1              124
 333 #define CYGNUM_HAL_INTERRUPT_RESERVED_125         125
 334 #define CYGNUM_HAL_INTERRUPT_RESERVED_126         126
 335 #define CYGNUM_HAL_INTERRUPT_RESERVED_127         127
 336
 337 #define CYGNUM_HAL_INTERRUPT_I2C_0                128
 338 #define CYGNUM_HAL_INTERRUPT_RESERVED_129       129
 339 #define CYGNUM_HAL_INTERRUPT_RESERVED_130       130
 340 #define CYGNUM_HAL_INTERRUPT_RESERVED_131       131
 341
 342 #define CYGNUM_HAL_INTERRUPT_I2C_1              132
 343 #define CYGNUM_HAL_INTERRUPT_RESERVED_133       133
 344 #define CYGNUM_HAL_INTERRUPT_RESERVED_134       134
 345 #define CYGNUM_HAL_INTERRUPT_RESERVED_135       135
 346
 347 #define CYGNUM_HAL_INTERRUPT_KEY                136
 348 #define CYGNUM_HAL_INTERRUPT_RESERVED_137       137
 349 #define CYGNUM_HAL_INTERRUPT_RESERVED_138       138
 350 #define CYGNUM_HAL_INTERRUPT_RESERVED_139       139
 351
 352 #define CYGNUM_HAL_INTERRUPT_IR_INPUT_0         140
 353 #define CYGNUM_HAL_INTERRUPT_RESERVED_141       141
 354 #define CYGNUM_HAL_INTERRUPT_RESERVED_142       142
 355 #define CYGNUM_HAL_INTERRUPT_RESERVED_143       143
 356
 357 #define CYGNUM_HAL_INTERRUPT_IR_INPUT_1         144
 358 #define CYGNUM_HAL_INTERRUPT_RESERVED_145       145
 359 #define CYGNUM_HAL_INTERRUPT_RESERVED_146       146
 360 #define CYGNUM_HAL_INTERRUPT_RESERVED_147       147
 361
 362 #define CYGNUM_HAL_INTERRUPT_IR_OUTPUT          148
 363 #define CYGNUM_HAL_INTERRUPT_RESERVED_149       149
 364 #define CYGNUM_HAL_INTERRUPT_RESERVED_150       150
 365 #define CYGNUM_HAL_INTERRUPT_RESERVED_151       151
 366
 367 #define CYGNUM_HAL_INTERRUPT_ICAM_0             152
 368 #define CYGNUM_HAL_INTERRUPT_RESERVED_153       153
 369 #define CYGNUM_HAL_INTERRUPT_RESERVED_154       154
 370 #define CYGNUM_HAL_INTERRUPT_RESERVED_155       155
 371
 372 #define CYGNUM_HAL_INTERRUPT_ICAM_1             156
 373 #define CYGNUM_HAL_INTERRUPT_RESERVED_157       157
 374 #define CYGNUM_HAL_INTERRUPT_RESERVED_158       158
 375 #define CYGNUM_HAL_INTERRUPT_RESERVED_159       159
 376
 377 #define CYGNUM_HAL_INTERRUPT_AFE                160
 378 #define CYGNUM_HAL_INTERRUPT_RESERVED_161       161
 379 #define CYGNUM_HAL_INTERRUPT_RESERVED_162       162
 380 #define CYGNUM_HAL_INTERRUPT_RESERVED_163       163
 381
 382 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_0         164
 383 #define CYGNUM_HAL_INTERRUPT_RESERVED_165       165
 384 #define CYGNUM_HAL_INTERRUPT_RESERVED_166       166
 385 #define CYGNUM_HAL_INTERRUPT_RESERVED_167       167
 386
 387 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_1         168
 388 #define CYGNUM_HAL_INTERRUPT_RESERVED_169       169
 389 #define CYGNUM_HAL_INTERRUPT_RESERVED_170       170
 390 #define CYGNUM_HAL_INTERRUPT_RESERVED_171       171
 391
 392 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_2         172
 393 #define CYGNUM_HAL_INTERRUPT_RESERVED_173       173
 394 #define CYGNUM_HAL_INTERRUPT_RESERVED_174       174
 395 #define CYGNUM_HAL_INTERRUPT_RESERVED_175       175
 396
 397 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_3         176
 398 #define CYGNUM_HAL_INTERRUPT_RESERVED_177       177
 399 #define CYGNUM_HAL_INTERRUPT_RESERVED_178       178
 400 #define CYGNUM_HAL_INTERRUPT_RESERVED_179       179
 401
 402 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_4         180
 403 #define CYGNUM_HAL_INTERRUPT_RESERVED_181       181
 404 #define CYGNUM_HAL_INTERRUPT_RESERVED_182       182
 405 #define CYGNUM_HAL_INTERRUPT_RESERVED_183       183
 406
 407 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_5         184
 408 #define CYGNUM_HAL_INTERRUPT_RESERVED_185       185
 409 #define CYGNUM_HAL_INTERRUPT_RESERVED_186       186
 410 #define CYGNUM_HAL_INTERRUPT_RESERVED_187       187
 411
 412 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_6         188
 413 #define CYGNUM_HAL_INTERRUPT_RESERVED_189       189
 414 #define CYGNUM_HAL_INTERRUPT_RESERVED_190       190
 415 #define CYGNUM_HAL_INTERRUPT_RESERVED_191       191
 416
 417 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_7         192
 418 #define CYGNUM_HAL_INTERRUPT_RESERVED_193       193
 419 #define CYGNUM_HAL_INTERRUPT_RESERVED_194       194
 420 #define CYGNUM_HAL_INTERRUPT_RESERVED_195       195
 421
 422 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_8         196
 423 #define CYGNUM_HAL_INTERRUPT_RESERVED_197       197
 424 #define CYGNUM_HAL_INTERRUPT_RESERVED_198       198
 425 #define CYGNUM_HAL_INTERRUPT_RESERVED_199       199
 426
 427 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_9         200
 428 #define CYGNUM_HAL_INTERRUPT_RESERVED_201       201
 429 #define CYGNUM_HAL_INTERRUPT_RESERVED_202       202
 430 #define CYGNUM_HAL_INTERRUPT_RESERVED_203       203
 431
 432 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_10        204
 433 #define CYGNUM_HAL_INTERRUPT_RESERVED_205       205
 434 #define CYGNUM_HAL_INTERRUPT_RESERVED_206       206
 435 #define CYGNUM_HAL_INTERRUPT_RESERVED_207       207
 436
 437 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_11        208
 438 #define CYGNUM_HAL_INTERRUPT_RESERVED_209       209
 439 #define CYGNUM_HAL_INTERRUPT_RESERVED_210       210
 440 #define CYGNUM_HAL_INTERRUPT_RESERVED_211       211
 441
 442 #define CYGNUM_HAL_INTERRUPT_EXTERNAL_12        212
 443 #define CYGNUM_HAL_INTERRUPT_RESERVED_213       213
 444 #define CYGNUM_HAL_INTERRUPT_RESERVED_214       214
 445 #define CYGNUM_HAL_INTERRUPT_RESERVED_215       215
 446
 447
 448 #define CYGNUM_HAL_ISR_MIN                     0
 449 #define CYGNUM_HAL_ISR_MAX                     215
 450
 451 #define CYGNUM_HAL_ISR_COUNT                   (3+((CYGNUM_HAL_ISR_MAX+1)/4))
 452
 453 // The vector used by the Real time clock
 454
 455 #define CYGNUM_HAL_INTERRUPT_RTC                CYGNUM_HAL_INTERRUPT_TIMER_5
 456
 457 //--------------------------------------------------------------------------
 458 // Interrupt vector translation.
 459
 460 #if !defined(HAL_TRANSLATE_VECTOR) && !defined(CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN)
 461
 462 #define HAL_TRANSLATE_VECTOR(_vector_,_index_)                             \
 463               _index_ = (((_vector_)<=CYGNUM_HAL_INTERRUPT_SYSTEM_ERROR) ? \
 464                          (_vector_) :                                      \
 465                          (((_vector_)>>2)+CYGNUM_HAL_INTERRUPT_RESERVED_3))
 466
 467 #endif
 468
 469 //--------------------------------------------------------------------------
 470 // AM33 specific version of HAL_INTERRUPT_CONFIGURE
 471
 472 #define HAL_INTERRUPT_CONFIGURE( _vector_, _level_, _up_ )                    \
 473 CYG_MACRO_START                                                               \
 474     if( (_vector_) >= CYGNUM_HAL_INTERRUPT_EXTERNAL_0 )                       \
 475     {                                                                         \
 476         cyg_uint32 _v_ = _vector_;                                            \
 477         cyg_uint16 _val_ = 0;                                                 \
 478         cyg_uint32 _reg_;                                                     \
 479                                                                               \
 480         /* adjust vector to bit offset in EXTMD */                            \
 481         _v_ -= CYGNUM_HAL_INTERRUPT_EXTERNAL_0;                               \
 482         _v_ >>= 1;                                                            \
 483                                                                               \
 484         /* set bits according to requirements */                              \
 485         if( _up_ ) _val_ |= 1;                                                \
 486         if( !(_level_) ) _val_ |= 2;                                          \
 487                                                                               \
 488         /* get EXTMD */                                                       \
 489         _reg_ = *(volatile cyg_uint32 *)&mn10300_interrupt_control[0x200>>1]; \
 490                                                                               \
 491         /* clear old value and set new */                                     \
 492         _reg_ &= ~(3<<_v_);                                                   \
 493         _reg_ |= _val_<<_v_;                                                  \
 494                                                                               \
 495         /* restore EXTMD */                                                   \
 496         *(volatile cyg_uint32 *)&mn10300_interrupt_control[0x200>>1] = _reg_; \
 497     }                                                                         \
 498 CYG_MACRO_END
 499
 500 #define HAL_INTERRUPT_CONFIGURE_DEFINED
 501
 502 //--------------------------------------------------------------------------
 503 // Timer control registers.
 504 // On the AM33 we use timers 4 and 5
 505
 506 #define TIMER4_CR        0xd40030a0
 507 #define TIMER4_BR        0xd4003090
 508 #define TIMER4_MD        0xd4003080
 509
 510 #define TIMER5_CR        0xd40030a2
 511 #define TIMER5_BR        0xd4003092
 512 #define TIMER5_MD        0xd4003082
 513
 514 //--------------------------------------------------------------------------
 515 // Clock control.
 516 extern cyg_uint32 __hal_period__;
 517
 518 #define HAL_CLOCK_INITIALIZE( _period_ )                                \
 519 {                                                                       \
 520     volatile cyg_uint16 *timer4_br      = (cyg_uint16 *)TIMER4_BR;      \
 521     volatile cyg_uint8 *timer4_md       = (cyg_uint8 *)TIMER4_MD;       \
 522     volatile cyg_uint16 *timer5_br      = (cyg_uint16 *)TIMER5_BR;      \
 523     volatile cyg_uint8 *timer5_md       = (cyg_uint8 *)TIMER5_MD;       \
 524                                                                         \
 525     /* Set timers 4 and 5 into cascade mode */                          \
 526                                                                         \
 527     *timer5_br = (_period_)>>16;                                        \
 528                                                                         \
 529     *timer5_md = 0x40;                                                  \
 530     *timer5_md = 0x83;                                                  \
 531                                                                         \
 532     *timer4_br = (_period_)&0x0000FFFF;                                 \
 533                                                                         \
 534     *timer4_md = 0x40;                                                  \
 535     *timer4_md = 0x80;                                                  \
 536                                                                         \
 537     __hal_period__ = _period_;                                          \
 538 }
 539
 540 #define HAL_CLOCK_RESET( _vector_, _period_ )
 541
 542 #define HAL_CLOCK_READ( _pvalue_ )                                      \
 543 {                                                                       \
 544     volatile cyg_uint16 *timer4_cr = (cyg_uint16 *)TIMER4_CR;           \
 545     volatile cyg_uint16 *timer5_cr = (cyg_uint16 *)TIMER5_CR;           \
 546                                                                         \
 547     cyg_uint16 t5;                                                      \
 548     cyg_uint16 t4;                                                      \
 549                                                                         \
 550     /* Loop reading the two timers until we can read t5 twice   */      \
 551     /* with the same value. This avoids getting silly times if  */      \
 552     /* the timers carry between reading the two regs.           */      \
 553     do {                                                                \
 554         t5 = *timer5_cr;                                                \
 555         t4 = *timer4_cr;                                                \
 556     } while( t5 != *timer5_cr );                                        \
 557                                                                         \
 558     *(_pvalue_) = __hal_period__ - ((t5<<16) + t4);                     \
 559 }
 560
 561 externC void hal_delay_us(cyg_int32 usecs);
 562
 563 #define HAL_DELAY_US(n)          hal_delay_us(n);
 564
 565
 566 //--------------------------------------------------------------------------
 567 #endif // ifndef CYGONCE_HAL_VAR_INTR_H
 568 // End of var_intr.h