1 #ifndef CYGONCE_HAL_HAL_IO_H
2 #define CYGONCE_HAL_HAL_IO_H
4 //=============================================================================
8 // HAL device IO register support.
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
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14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
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30 // or inline functions from this file, or you compile this file and link it
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41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
47 // Contributors: nickg, dmoseley
49 // Purpose: Define IO register support
50 // Description: The macros defined here provide the HAL APIs for handling
51 // device IO control registers.
54 // #include <cyg/hal/hal_io.h>
58 //####DESCRIPTIONEND####
60 //=============================================================================
63 #include <cyg/infra/cyg_type.h>
64 #include <cyg/hal/plf_io.h>
67 //-----------------------------------------------------------------------------
68 // IO Register address.
69 // This type is for recording the address of an IO register.
72 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
75 //-----------------------------------------------------------------------------
76 // BYTE Register access.
77 // Individual and vectorized access to 8 bit registers.
79 #define HAL_READ_UINT8( _register_, _value_ ) \
80 ((_value_) = *((volatile CYG_BYTE *)(_register_)))
82 #define HAL_WRITE_UINT8( _register_, _value_ ) \
83 (*((volatile CYG_BYTE *)(_register_)) = (_value_))
85 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
87 cyg_count32 _i_,_j_; \
88 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
89 (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_]; \
92 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ ) \
94 cyg_count32 _i_,_j_; \
95 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
96 ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_]; \
100 //-----------------------------------------------------------------------------
102 // Individual and vectorized access to 16 bit registers.
104 #define HAL_READ_UINT16( _register_, _value_ ) \
105 ((_value_) = *((volatile CYG_WORD16 *)(_register_)))
107 #define HAL_WRITE_UINT16( _register_, _value_ ) \
108 (*((volatile CYG_WORD16 *)(_register_)) = (_value_))
110 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
112 cyg_count32 _i_,_j_; \
113 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
114 (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_]; \
117 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ ) \
119 cyg_count32 _i_,_j_; \
120 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
121 ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_]; \
124 //-----------------------------------------------------------------------------
126 // Individual and vectorized access to 32 bit registers.
128 #define HAL_READ_UINT32( _register_, _value_ ) \
129 ((_value_) = *((volatile CYG_WORD32 *)(_register_)))
131 #define HAL_WRITE_UINT32( _register_, _value_ ) \
132 (*((volatile CYG_WORD32 *)(_register_)) = (_value_))
134 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
136 cyg_count32 _i_,_j_; \
137 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
138 (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_]; \
141 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ ) \
143 cyg_count32 _i_,_j_; \
144 for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) \
145 ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_]; \
148 //-----------------------------------------------------------------------------
149 #endif // ifndef CYGONCE_HAL_HAL_IO_H