1 #ifndef CYGONCE_HAL_PLATFORM_INC
2 #define CYGONCE_HAL_PLATFORM_INC
3 ##=============================================================================
7 ## ASB2303 board assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 ## eCos is free software; you can redistribute it and/or modify it under
16 ## the terms of the GNU General Public License as published by the Free
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20 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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25 ## with eCos; if not, write to the Free Software Foundation, Inc.,
26 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 ## As a special exception, if other files instantiate templates or use macros
29 ## or inline functions from this file, or you compile this file and link it
30 ## with other works to produce a work based on this file, this file does not
31 ## by itself cause the resulting work to be covered by the GNU General Public
32 ## License. However the source code for this file must still be made available
33 ## in accordance with section (3) of the GNU General Public License.
35 ## This exception does not invalidate any other reasons why a work based on
36 ## this file might be covered by the GNU General Public License.
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39 ## at http://sources.redhat.com/ecos/ecos-license/
40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
45 ## Author(s): dmoseley
46 ## Contributors:dmoseley
48 ## Purpose: ASB board definitions.
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the ASB board.
52 ## #include <cyg/hal/platform.inc>
56 ######DESCRIPTIONEND####
58 ##=============================================================================
60 #include <pkgconf/hal.h>
61 #include <cyg/hal/plf_io.h>
63 #------------------------------------------------------------------------------
66 #include <cyg/hal/hal_io.h>
69 .globl hal_diag_led_state
70 hal_diag_led_state: .long 0xffffffff
71 hal_diag_intr_count: .long 0
74 #define HAL_EARLY_INIT hal_led_init
76 # Setup Port 0 as all output
77 # Do this the very first thing so we have LED debugging available early
78 mov HAL_GPIO_MODE_ALL_OUTPUT,d0
79 mov HAL_GPIO_0_MODE,a0
106 .ascii "0123456789ABCDEF"
112 .macro hal_diag_excpt_start
113 mov HAL_LED_ADDRESS,a0
119 .macro hal_diag_intr_start
120 mov (hal_diag_intr_count),d1
125 mov HAL_LED_ADDRESS,a0
130 mov d1,(hal_diag_intr_count)
133 .macro hal_diag_restore
134 mov (hal_diag_intr_count),d0
137 mov HAL_LED_ADDRESS,a0
144 .macro hal_diag_led val
146 0: mov hal_diag_digits,a2
151 mov HAL_LED_ADDRESS,a2
159 #define CYGPKG_HAL_MN10300_DIAG_DEFINED
161 #------------------------------------------------------------------------------
164 #ifndef CYGPKG_HAL_MN10300_MEMC_DEFINED
166 // These settings follow the recommended settings in the
167 // "MN103E010 Evaluation Board User's Guide"
169 #define BCCR 0xC0002000
170 #define BCCR_INIT 0x12040580
172 #define SBBASE0 0xD8C00100
173 #define SBBASE1 0xD8C00110
174 #define SBBASE2 0xD8C00120
175 #define SBBASE3 0xD8C00130
176 #define SBBASE4 0xD8C00140
177 #define SBBASE5 0xD8C00150
178 #define SBBASE6 0xD8C00160
179 #define SBBASE7 0xD8C00170
181 #define SBBASE0_INIT_SYSFL 0x8000FE01
182 #define SBBASE0_INIT_BPROM 0x8400FE01
183 #define SBBASE1_INIT_SYSFL 0x8400FE01
184 #define SBBASE1_INIT_BPROM 0x8000FE01
185 #define SBBASE2_INIT 0x8600FF81
186 #define SBBASE3_INIT 0x00000000
187 #define SBBASE4_INIT 0x00000000
188 #define SBBASE5_INIT 0x00000000
189 #define SBBASE6_INIT 0x00000000
190 #define SBBASE7_INIT 0x00000000
192 #define SBCTRL00 0xD8C00200
193 #define SBCTRL10 0xD8C00210
194 #define SBCTRL20 0xD8C00220
195 #define SBCTRL30 0xD8C00230
196 #define SBCTRL40 0xD8C00240
197 #define SBCTRL50 0xD8C00250
198 #define SBCTRL60 0xD8C00260
199 #define SBCTRL70 0xD8C00270
201 #define SBCTRL00_INIT 0x21111000
202 #define SBCTRL10_INIT 0x21111000
203 #define SBCTRL20_INIT 0x21111000
204 #define SBCTRL30_INIT 0x00000000
205 #define SBCTRL40_INIT 0x00000000
206 #define SBCTRL50_INIT 0x00000000 // 0x21111100
207 #define SBCTRL60_INIT 0x00000000 // 0x11110000
208 #define SBCTRL70_INIT 0x00000000
210 #define SBCTRL01 0xD8C00204
211 #define SBCTRL11 0xD8C00214
212 #define SBCTRL21 0xD8C00224
213 #define SBCTRL31 0xD8C00234
214 #define SBCTRL41 0xD8C00244
215 #define SBCTRL51 0xD8C00254
216 #define SBCTRL61 0xD8C00264
217 #define SBCTRL71 0xD8C00274
219 #define SBCTRL01_INIT 0x00100200
220 #define SBCTRL11_INIT 0x00100200
221 #define SBCTRL21_INIT 0x00100200
222 #define SBCTRL31_INIT 0x00000000
223 #define SBCTRL41_INIT 0x00000000
224 #define SBCTRL51_INIT 0x00000000
225 #define SBCTRL61_INIT 0x00000000
226 #define SBCTRL71_INIT 0x00000000
228 #define SBCTRL02 0xD8C00208
229 #define SBCTRL12 0xD8C00218
230 #define SBCTRL22 0xD8C00228
231 #define SBCTRL32 0xD8C00238
232 #define SBCTRL42 0xD8C00248
233 #define SBCTRL52 0xD8C00258
234 #define SBCTRL62 0xD8C00268
235 #define SBCTRL72 0xD8C00278
237 #define SBCTRL02_INIT 0x00000004
238 #define SBCTRL12_INIT 0x04000004
239 #define SBCTRL22_INIT 0x00000004
240 #define SBCTRL32_INIT 0x00000000
241 #define SBCTRL42_INIT 0x00000000
242 #define SBCTRL52_INIT 0x00000000
243 #define SBCTRL62_INIT 0x00000000
244 #define SBCTRL72_INIT 0x00000000
246 #define SDBASE0 0xDA000008
247 #define SDBASE1 0xDA00000C
248 #define SDRAMBUS 0xDA000000
251 #define SDBASE0_8M_INIT 0x9000FF81
252 #define SDBASE1_8M_INIT 0x9080FF81
253 #define SDRAMBUS_8M_INIT 0xA8990654
256 #define SDBASE0_16M_INIT 0x9000FF01
257 #define SDBASE1_16M_INIT 0x9100FF01
258 #define SDRAMBUS_16M_INIT 0xA89a0654
261 #define SDBASE0_32M_INIT 0x9000fe01
262 #define SDBASE1_32M_INIT 0x9200fe01
263 #define SDRAMBUS_32M_INIT 0xa89b0654
270 // reduce the span of the ROM banks first
404 #ifndef CYG_HAL_STARTUP_RAM
406 // Setup for 64MB initially and determine final mem config below.
409 and 0xfffffffb,d0 // disable refresh
413 mov SDBASE0_32M_INIT,d0
416 mov SDBASE1_32M_INIT,d0
419 mov SDRAMBUS_32M_INIT,d0
427 // Check for 16MB and 32MB shadowing to determine actual amount of
428 // memory installed. This assumes 2x8M, 2x16M, or 2x32M configs.
441 and 0xfffffffb,d0 // disable refresh
444 mov SDBASE0_8M_INIT,d1
447 mov SDBASE1_8M_INIT,d1
449 mov SDRAMBUS_8M_INIT,d0
460 and 0xfffffffb,d0 // disable refresh
463 mov SDBASE0_16M_INIT,d1
466 mov SDBASE1_16M_INIT,d1
468 mov SDRAMBUS_16M_INIT,d0
471 #endif // ! CYG_HAL_STARTUP_RAM
473 // now the ROMs need putting into the right place
474 // - this is tricky because when we're booting from the system flash,
475 // it has had its base address pre-swapped by the CPU
476 // - we need to copy a small piece of code to the SRAM and execute it
479 // copy the ROM address adjustor to the SRAM
483 add __hal_plf_rom_swap_start-__hal_plf_base_ref,a0
484 add __hal_plf_rom_swap_end-__hal_plf_base_ref,a3
495 ////////////////////////////////////////////////////////////////
496 __hal_plf_rom_swap_start:
497 // put boot PROM at 0x80000000, and system flash at 0x84000000
498 mov SBBASE0_INIT_BPROM,d0
501 mov SBBASE1_INIT_BPROM,d0
520 // jump forward so we start running from the 80000000/84000000 base address
521 mov __hal_plf_rom_swap_reentry,a0
523 __hal_plf_rom_swap_end:
524 ////////////////////////////////////////////////////////////////
526 __hal_plf_rom_swap_reentry:
527 // clear the on-CPU 16Kb SRAM
538 #define CYGPKG_HAL_MN10300_MEMC_DEFINED
543 //-----------------------------------------------------------------------------
545 // RedBoot provides syscall handling for this board
546 // These must be kept in sync with the rest of the tree.
548 #define SIGSYSCALL SIGSYS
550 #------------------------------------------------------------------------------
551 #endif // ifndef CYGONCE_HAL_PLATFORM_INC
552 # end of platform.inc