packages/hal/powerpc/arch/v2_0/include/hal_io.h

   1 #ifndef CYGONCE_HAL_IO_H
   2 #define CYGONCE_HAL_IO_H
   3
   4 //=============================================================================
   5 //
   6 //      hal_io.h
   7 //
   8 //      HAL device IO register support.
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 // Copyright (C) 2002, 2003 Gary Thomas
  16 //
  17 // eCos is free software; you can redistribute it and/or modify it under
  18 // the terms of the GNU General Public License as published by the Free
  19 // Software Foundation; either version 2 or (at your option) any later version.
  20 //
  21 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  22 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  23 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  24 // for more details.
  25 //
  26 // You should have received a copy of the GNU General Public License along
  27 // with eCos; if not, write to the Free Software Foundation, Inc.,
  28 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  29 //
  30 // As a special exception, if other files instantiate templates or use macros
  31 // or inline functions from this file, or you compile this file and link it
  32 // with other works to produce a work based on this file, this file does not
  33 // by itself cause the resulting work to be covered by the GNU General Public
  34 // License. However the source code for this file must still be made available
  35 // in accordance with section (3) of the GNU General Public License.
  36 //
  37 // This exception does not invalidate any other reasons why a work based on
  38 // this file might be covered by the GNU General Public License.
  39 //
  40 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  41 // at http://sources.redhat.com/ecos/ecos-license/
  42 // -------------------------------------------
  43 //####ECOSGPLCOPYRIGHTEND####
  44 //=============================================================================
  45 //#####DESCRIPTIONBEGIN####
  46 //
  47 // Author(s):   nickg
  48 // Contributors:        nickg
  49 // Date:        1998-02-17
  50 // Purpose:     Define IO register support
  51 // Description: The macros defined here provide the HAL APIs for handling
  52 //              device IO control registers.
  53 //
  54 // Usage:
  55 //              #include <cyg/hal/hal_io.h>
  56 //              ...
  57 //
  58 //
  59 //####DESCRIPTIONEND####
  60 //
  61 //=============================================================================
  62
  63 #include <cyg/infra/cyg_type.h>
  64 #ifdef CYGBLD_HAL_VAR_IO_H
  65 #include CYGBLD_HAL_VAR_IO_H
  66 #endif
  67 #ifdef CYGBLD_HAL_PLF_IO_H
  68 #include CYGBLD_HAL_PLF_IO_H
  69 #endif
  70
  71 //-----------------------------------------------------------------------------
  72 // Enforce in-order IO for all HAL reads/writes using this macro.
  73 #define HAL_IO_BARRIER()                        \
  74     asm volatile ( "eieio" : : : "memory" )
  75
  76 //-----------------------------------------------------------------------------
  77 // IO Register address.
  78 // This type is for recording the address of an IO register.
  79
  80 typedef volatile CYG_ADDRWORD HAL_IO_REGISTER;
  81
  82 //-----------------------------------------------------------------------------
  83 // BYTE Register access.
  84 // Individual and vectorized access to 8 bit registers.
  85
  86 #define HAL_READ_UINT8( _register_, _value_ )           \
  87     CYG_MACRO_START                                     \
  88     ((_value_) = *((volatile CYG_BYTE *)(_register_))); \
  89     HAL_IO_BARRIER ();                                  \
  90     CYG_MACRO_END
  91
  92 #define HAL_WRITE_UINT8( _register_, _value_ )          \
  93     CYG_MACRO_START                                     \
  94     (*((volatile CYG_BYTE *)(_register_)) = (_value_)); \
  95     HAL_IO_BARRIER ();                                  \
  96     CYG_MACRO_END
  97
  98 #define HAL_READ_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )     \
  99     CYG_MACRO_START                                                     \
 100     cyg_count32 _i_,_j_;                                                \
 101     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 102         (_buf_)[_i_] = ((volatile CYG_BYTE *)(_register_))[_j_];        \
 103         HAL_IO_BARRIER ();                                              \
 104     }                                                                   \
 105     CYG_MACRO_END
 106
 107 #define HAL_WRITE_UINT8_VECTOR( _register_, _buf_, _count_, _step_ )    \
 108     CYG_MACRO_START                                                     \
 109     cyg_count32 _i_,_j_;                                                \
 110     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 111         ((volatile CYG_BYTE *)(_register_))[_j_] = (_buf_)[_i_];        \
 112         HAL_IO_BARRIER ();                                              \
 113     }                                                                   \
 114     CYG_MACRO_END
 115
 116
 117 //-----------------------------------------------------------------------------
 118 // 16 bit access.
 119 // Individual and vectorized access to 16 bit registers.
 120
 121 #define HAL_READ_UINT16( _register_, _value_ )                  \
 122     CYG_MACRO_START                                             \
 123     ((_value_) = *((volatile CYG_WORD16 *)(_register_)));       \
 124     HAL_IO_BARRIER ();                                          \
 125     CYG_MACRO_END
 126
 127 #define HAL_WRITE_UINT16( _register_, _value_ )                 \
 128     CYG_MACRO_START                                             \
 129     (*((volatile CYG_WORD16 *)(_register_)) = (_value_));       \
 130     HAL_IO_BARRIER ();                                          \
 131     CYG_MACRO_END
 132
 133 #define HAL_READ_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )    \
 134     CYG_MACRO_START                                                     \
 135     cyg_count32 _i_,_j_;                                                \
 136     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 137         (_buf_)[_i_] = ((volatile CYG_WORD16 *)(_register_))[_j_];      \
 138         HAL_IO_BARRIER ();                                              \
 139     }                                                                   \
 140     CYG_MACRO_END
 141
 142 #define HAL_WRITE_UINT16_VECTOR( _register_, _buf_, _count_, _step_ )   \
 143     CYG_MACRO_START                                                     \
 144     cyg_count32 _i_,_j_;                                                \
 145     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 146         ((volatile CYG_WORD16 *)(_register_))[_j_] = (_buf_)[_i_];      \
 147         HAL_IO_BARRIER ();                                              \
 148     }                                                                   \
 149     CYG_MACRO_END
 150
 151 //-----------------------------------------------------------------------------
 152 // 32 bit access.
 153 // Individual and vectorized access to 32 bit registers.
 154
 155 #define HAL_READ_UINT32( _register_, _value_ )                  \
 156     CYG_MACRO_START                                             \
 157     ((_value_) = *((volatile CYG_WORD32 *)(_register_)));       \
 158     HAL_IO_BARRIER ();                                          \
 159     CYG_MACRO_END
 160
 161 #define HAL_WRITE_UINT32( _register_, _value_ )                 \
 162     CYG_MACRO_START                                             \
 163     (*((volatile CYG_WORD32 *)(_register_)) = (_value_));       \
 164     HAL_IO_BARRIER ();                                          \
 165     CYG_MACRO_END
 166
 167 #define HAL_READ_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )    \
 168     CYG_MACRO_START                                                     \
 169     cyg_count32 _i_,_j_;                                                \
 170     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 171         (_buf_)[_i_] = ((volatile CYG_WORD32 *)(_register_))[_j_];      \
 172         HAL_IO_BARRIER ();                                              \
 173     }                                                                   \
 174     CYG_MACRO_END
 175
 176 #define HAL_WRITE_UINT32_VECTOR( _register_, _buf_, _count_, _step_ )   \
 177     CYG_MACRO_START                                                     \
 178     cyg_count32 _i_,_j_;                                                \
 179     for( _i_ = 0, _j_ = 0; _i_ < (_count_); _i_++, _j_ += (_step_)) {   \
 180         ((volatile CYG_WORD32 *)(_register_))[_j_] = (_buf_)[_i_];      \
 181         HAL_IO_BARRIER ();                                              \
 182     }                                                                   \
 183     CYG_MACRO_END
 184
 185 //-----------------------------------------------------------------------------
 186 #endif // ifndef CYGONCE_HAL_IO_H
 187 // End of hal_io.h