1 //========================================================================
5 // Helper functions for stub, generic to all PowerPC processors
7 //========================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //========================================================================
41 //#####DESCRIPTIONBEGIN####
43 // Author(s): Red Hat, jskov
44 // Contributors: Red Hat, jskov, gthomas
47 // Description: Helper functions for stub, generic to all PowerPC processors
50 //####DESCRIPTIONEND####
52 //========================================================================
56 #include <pkgconf/hal.h>
58 #ifdef CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS
60 #define CYGARC_HAL_COMMON_EXPORT_CPU_MACROS
61 #include <cyg/hal/ppc_regs.h>
63 #include <cyg/hal/hal_stub.h>
64 #include <cyg/hal/hal_arch.h>
65 #include <cyg/hal/hal_intr.h>
67 #ifdef CYGNUM_HAL_NO_VECTOR_TRACE
68 #define USE_BREAKPOINTS_FOR_SINGLE_STEP
71 #ifdef CYGDBG_HAL_DEBUG_GDB_THREAD_SUPPORT
72 #include <cyg/hal/dbg-threads-api.h> // dbg_currthread_id
76 #define OFFSETOF(_struct_, _member_) (int)((char *)(&(((_struct_*)0)->_member_))-(char *)((_struct_*)0))
79 /* Given a trap value TRAP, return the corresponding signal. */
81 int __computeSignal (unsigned int trap_number)
85 case CYGNUM_HAL_VECTOR_MACHINE_CHECK:
87 case CYGNUM_HAL_VECTOR_DSI:
91 case CYGNUM_HAL_VECTOR_ISI:
92 /* Instruction access (Ifetch) */
93 case CYGNUM_HAL_VECTOR_ALIGNMENT:
97 case CYGNUM_HAL_VECTOR_INTERRUPT:
98 /* External interrupt */
101 case CYGNUM_HAL_VECTOR_TRACE:
102 /* Instruction trace */
105 case CYGNUM_HAL_VECTOR_PROGRAM:
106 #ifdef CYGPKG_HAL_POWERPC_PPC40x
107 // The 40x is b0rken, returning 0 for these bits. Translate to
108 // SIGTRAP to allow thread debugging.
111 // The register PS contains the value of SRR1 at the time of
112 // exception entry. Bits 11-15 contain information about the
113 // cause of the exception. Bits 16-31 the PS (MSR) state.
114 #ifdef USE_BREAKPOINTS_FOR_SINGLE_STEP
115 if (__is_single_step(get_register(PC))) {
119 switch ((get_register (PS) >> 17) & 0xf){
122 case 2: /* privileged instruction */
123 case 4: /* illegal instruction */
125 case 8: /* floating point */
127 default: /* should never happen! */
132 case CYGNUM_HAL_VECTOR_RESERVED_A:
133 case CYGNUM_HAL_VECTOR_RESERVED_B:
136 case CYGNUM_HAL_VECTOR_FP_UNAVAILABLE:
138 case CYGNUM_HAL_VECTOR_FP_ASSIST:
142 case CYGNUM_HAL_VECTOR_DECREMENTER:
143 /* Decrementer alarm */
146 case CYGNUM_HAL_VECTOR_SYSTEM_CALL:
150 #if defined(CYGPKG_HAL_POWERPC_MPC8xx) || defined(CYGPKG_HAL_POWERPC_MPC5xx)
151 case CYGNUM_HAL_VECTOR_SW_EMUL:
152 /* A SW_EMUL is generated instead of PROGRAM for illegal
156 case CYGNUM_HAL_VECTOR_DATA_BP:
157 case CYGNUM_HAL_VECTOR_INSTRUCTION_BP:
158 case CYGNUM_HAL_VECTOR_PERIPHERAL_BP:
159 case CYGNUM_HAL_VECTOR_NMI:
160 /* Developer port debugging exceptions. */
163 #if defined(CYGNUM_HAL_VECTOR_ITLB_MISS)
164 case CYGNUM_HAL_VECTOR_ITLB_MISS:
165 /* Software reload of TLB required. */
168 #if defined(CYGNUM_HAL_VECTOR_DTLB_MISS)
169 case CYGNUM_HAL_VECTOR_DTLB_MISS:
170 /* Software reload of TLB required. */
173 case CYGNUM_HAL_VECTOR_ITLB_ERROR:
174 /* Invalid instruction access. */
177 case CYGNUM_HAL_VECTOR_DTLB_ERROR:
178 /* Invalid data access. */
180 #endif // defined(CYGPKG_HAL_POWERPC_MPC8xx)
188 /* Return the trap number corresponding to the last-taken trap. */
190 int __get_trap_number (void)
192 // The vector is not not part of the GDB register set so get it
193 // directly from the save context.
194 return _hal_registers->vector >> 8;
197 /* Set the currently-saved pc register value to PC. This also updates NPC
200 void set_pc (target_register_t pc)
202 put_register (PC, pc);
205 #ifdef CYGHWR_HAL_POWERPC_FPU
207 reg_offset(regnames_t reg)
209 // We let the compiler determine the offsets in order to avoid all
210 // possible alignment problems
212 // 32 general purpose registers
213 if(reg < F0) return reg * 4;
215 // first sixteen floating point regs
216 base_offset = OFFSETOF(GDB_Registers, f0);
217 if(reg < F16) return base_offset + ((reg - F0) * 8);
219 // last sixteen floating point regs
220 base_offset = OFFSETOF(GDB_Registers, f16);
221 if(reg < PC) return base_offset + ((reg - F16) * 8);
224 if(reg < PS) return(OFFSETOF(GDB_Registers, pc));
225 if(reg < CND) return(OFFSETOF(GDB_Registers, msr));
226 if(reg < LR) return(OFFSETOF(GDB_Registers, cr));
227 if(reg < CNT) return(OFFSETOF(GDB_Registers, lr));
228 if(reg < XER) return(OFFSETOF(GDB_Registers, ctr));
229 if(reg < MQ) return(OFFSETOF(GDB_Registers, xer));
231 return OFFSETOF(GDB_Registers, mq);
234 // Return the currently-saved value corresponding to register REG of
235 // the exception context.
237 get_register (regnames_t reg)
239 target_register_t val;
240 int offset = reg_offset(reg);
242 if (REGSIZE(reg) > sizeof(target_register_t))
245 val = _registers[offset/sizeof(target_register_t)];
250 // Store VALUE in the register corresponding to WHICH in the exception
253 put_register (regnames_t which, target_register_t value)
255 int offset = reg_offset(which);
257 if (REGSIZE(which) > sizeof(target_register_t))
260 _registers[offset/sizeof(target_register_t)] = value;
263 // Write the contents of register WHICH into VALUE as raw bytes. This
264 // is only used for registers larger than sizeof(target_register_t).
265 // Return non-zero if it is a valid register.
267 get_register_as_bytes (regnames_t which, char *value)
269 int offset = reg_offset(which);
271 memcpy (value, (char *)_registers + offset, REGSIZE(which));
275 // Alter the contents of saved register WHICH to contain VALUE. This
276 // is only used for registers larger than sizeof(target_register_t).
277 // Return non-zero if it is a valid register.
279 put_register_as_bytes (regnames_t which, char *value)
281 int offset = reg_offset(which);
283 memcpy ((char *)_registers + offset, value, REGSIZE(which));
288 /*----------------------------------------------------------------------
289 * Single-step support
292 /* Set things up so that the next user resume will execute one instruction.
293 This may be done by setting breakpoints or setting a single step flag
294 in the saved user registers, for example. */
296 #ifdef USE_BREAKPOINTS_FOR_SINGLE_STEP
298 #if (HAL_BREAKINST_SIZE == 1)
299 typedef cyg_uint8 t_inst;
300 #elif (HAL_BREAKINST_SIZE == 2)
301 typedef cyg_uint16 t_inst;
302 #elif (HAL_BREAKINST_SIZE == 4)
303 typedef cyg_uint32 t_inst;
305 #error "Don't know how to handle that size"
314 static instrBuffer sstep_instr[2];
315 static target_register_t irq_state = 0;
318 __insert_break(int indx, target_register_t pc)
320 sstep_instr[indx].targetAddr = (t_inst *)pc;
321 sstep_instr[indx].savedInstr = *(t_inst *)pc;
322 *(t_inst*)pc = (t_inst)HAL_BREAKINST;
323 __data_cache(CACHE_FLUSH);
324 __instruction_cache(CACHE_FLUSH);
328 __remove_break(int indx)
330 if (sstep_instr[indx].targetAddr != 0) {
331 *(sstep_instr[indx].targetAddr) = sstep_instr[indx].savedInstr;
332 sstep_instr[indx].targetAddr = 0;
333 __data_cache(CACHE_FLUSH);
334 __instruction_cache(CACHE_FLUSH);
339 __is_single_step(target_register_t pc)
341 return (sstep_instr[0].targetAddr == (t_inst *)pc) ||
342 (sstep_instr[1].targetAddr == (t_inst *)pc);
346 // Compute the target address for this instruction, if the instruction
347 // is some sort of branch/flow change.
353 unsigned int reserved : 5;
354 unsigned int xo : 10;
381 static target_register_t
382 __branch_pc(target_register_t pc)
386 insn.word = *(t_inst *)pc;
388 // Decode the instruction to determine the instruction which will follow
389 // Note: there are holes in this process, but the important ones work
394 return (target_register_t)(insn.b.bd << 2);
396 return (target_register_t)((insn.b.bd << 2) + (long)pc);
401 return (target_register_t)(insn.i.li << 2);
403 return (target_register_t)((insn.i.li << 2) + (long)pc);
406 if (insn.xl.reserved == 0) {
407 if (insn.xl.xo == 528) {
409 return (target_register_t)(get_register(CNT) & ~3);
410 } else if (insn.xl.xo == 16) {
412 return (target_register_t)(get_register(LR) & ~3);
422 void __single_step(void)
424 target_register_t msr = get_register(PS);
425 target_register_t pc = get_register(PC);
426 target_register_t next_pc = __branch_pc(pc);
428 // Disable interrupts.
429 irq_state = msr & MSR_EE;
431 put_register (PS, msr);
433 // Set a breakpoint at the next instruction
434 __insert_break(0, pc+4);
435 if (next_pc != (pc+4)) {
436 __insert_break(1, next_pc);
440 /* Clear the single-step state. */
442 void __clear_single_step(void)
444 target_register_t msr = get_register (PS);
446 // Restore interrupt state.
447 // FIXME: Should check whether the executed instruction changed the
448 // interrupt state - or single-stepping a MSR changing instruction
449 // may result in a wrong EE. Not a very likely scenario though.
452 // This function is called much more than its counterpart
453 // __single_step. Only re-enable interrupts if they where
454 // disabled during the previous cal to __single_step. Otherwise,
455 // this function only makes "extra sure" that no trace or branch
456 // exception will happen.
459 put_register (PS, msr);
461 // Remove breakpoints
468 static target_register_t irq_state = 0;
470 void __single_step (void)
472 target_register_t msr = get_register (PS);
474 // Set single-step flag in the exception context.
475 msr |= (MSR_SE | MSR_BE);
476 // Disable interrupts.
477 irq_state = msr & MSR_EE;
480 put_register (PS, msr);
483 /* Clear the single-step state. */
485 void __clear_single_step (void)
487 target_register_t msr = get_register (PS);
489 // Clear single-step flag in the exception context.
490 msr &= ~(MSR_SE | MSR_BE);
491 // Restore interrupt state.
492 // FIXME: Should check whether the executed instruction changed the
493 // interrupt state - or single-stepping a MSR changing instruction
494 // may result in a wrong EE. Not a very likely scenario though.
497 // This function is called much more than its counterpart
498 // __single_step. Only re-enable interrupts if they where
499 // disabled during the previous cal to __single_step. Otherwise,
500 // this function only makes "extra sure" that no trace or branch
501 // exception will happen.
504 put_register (PS, msr);
508 void __install_breakpoints (void)
510 /* NOP since single-step HW exceptions are used instead of
514 void __clear_breakpoints (void)
519 /* If the breakpoint we hit is in the breakpoint() instruction, return a
523 __is_breakpoint_function ()
525 return get_register (PC) == (target_register_t)&_breakinst;
529 /* Skip the current instruction. Since this is only called by the
530 stub when the PC points to a breakpoint or trap instruction,
531 we can safely just skip 4. */
533 void __skipinst (void)
535 put_register (PC, get_register (PC) + 4);
538 #endif // CYGDBG_HAL_DEBUG_GDB_INCLUDE_STUBS