packages/hal/powerpc/mpc8xx/v2_0/include/var_cache.h

   1 #ifndef CYGONCE_VAR_CACHE_H
   2 #define CYGONCE_VAR_CACHE_H
   3 //=============================================================================
   4 //
   5 //      var_cache.h
   6 //
   7 //      Variant HAL cache control API
   8 //
   9 //=============================================================================
  10 //####ECOSGPLCOPYRIGHTBEGIN####
  11 // -------------------------------------------
  12 // This file is part of eCos, the Embedded Configurable Operating System.
  13 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  14 // Copyright (C) 2003 Gary Thomas
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):   nickg
  47 // Contributors:nickg, jskov
  48 // Date:        2000-04-02
  49 // Purpose:     Variant cache control API
  50 // Description: The macros defined here provide the HAL APIs for handling
  51 //              cache control operations on the MPC8xx variant CPUs.
  52 // Usage:       Is included via the architecture cache header:
  53 //              #include <cyg/hal/hal_cache.h>
  54 //              ...
  55 //
  56 //####DESCRIPTIONEND####
  57 //
  58 //=============================================================================
  59
  60 #include <pkgconf/hal.h>
  61 #include <cyg/infra/cyg_type.h>
  62
  63 #include <cyg/hal/ppc_regs.h>
  64
  65 #include <cyg/hal/plf_cache.h>
  66
  67
  68 //-----------------------------------------------------------------------------
  69 // Cache dimensions - these vary between the 8xx sub-models
  70
  71 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_862P)
  72 // Data cache
  73 #define HAL_DCACHE_SIZE                 (8*1024)    // Size of data cache in bytes
  74 #define HAL_DCACHE_LINE_SIZE            16          // Size of a data cache line
  75 #define HAL_DCACHE_WAYS                 2           // Associativity of the cache
  76
  77 // Instruction cache
  78 #define HAL_ICACHE_SIZE                 (16*1024)   // Size of cache in bytes
  79 #define HAL_ICACHE_LINE_SIZE            16          // Size of a cache line
  80 #define HAL_ICACHE_WAYS                 2           // Associativity of the cache
  81 #endif // defined(CYGHWR_HAL_POWERPC_MPC862P)
  82
  83 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_860) || \
  84     defined(CYGHWR_HAL_POWERPC_MPC8XX_860T) || \
  85     defined(CYGHWR_HAL_POWERPC_MPC8XX_862T) || \
  86     defined(CYGHWR_HAL_POWERPC_MPC8XX_866T) || \
  87     defined(CYGHWR_HAL_POWERPC_MPC8XX_855T) || \
  88     defined(CYGHWR_HAL_POWERPC_MPC8XX_852T)
  89 // Data cache
  90 #define HAL_DCACHE_SIZE                 4096    // Size of data cache in bytes
  91 #define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
  92 #define HAL_DCACHE_WAYS                 2       // Associativity of the cache
  93
  94 // Instruction cache
  95 #define HAL_ICACHE_SIZE                 4096    // Size of cache in bytes
  96 #define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
  97 #define HAL_ICACHE_WAYS                 2       // Associativity of the cache
  98 #endif // defined(CYGHWR_HAL_POWERPC_MPC860)
  99
 100 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || \
 101     defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
 102 // Data cache
 103 #define HAL_DCACHE_SIZE                 1024    // Size of data cache in bytes
 104 #define HAL_DCACHE_LINE_SIZE            16      // Size of a data cache line
 105 #define HAL_DCACHE_WAYS                 2       // Associativity of the cache
 106
 107 // Instruction cache
 108 #define HAL_ICACHE_SIZE                 2048    // Size of cache in bytes
 109 #define HAL_ICACHE_LINE_SIZE            16      // Size of a cache line
 110 #define HAL_ICACHE_WAYS                 2       // Associativity of the cache
 111 #endif // defined(CYGHWR_HAL_POWERPC_MPC8XX_823) || defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
 112
 113 #ifndef HAL_ICACHE_SIZE
 114 #error Missing cache definitions for this processor?
 115 #endif
 116
 117 #define HAL_DCACHE_SETS (HAL_DCACHE_SIZE/(HAL_DCACHE_LINE_SIZE*HAL_DCACHE_WAYS))
 118 #define HAL_ICACHE_SETS (HAL_ICACHE_SIZE/(HAL_ICACHE_LINE_SIZE*HAL_ICACHE_WAYS))
 119
 120 //-----------------------------------------------------------------------------
 121 // Global control of data cache
 122
 123 // Enable the data cache
 124 #define HAL_DCACHE_ENABLE()                     \
 125     asm volatile ("sync;"                       \
 126                   "mtspr %0, %1;"               \
 127                   : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CE))
 128
 129 // Disable the data cache
 130 #define HAL_DCACHE_DISABLE()                    \
 131     asm volatile ("sync;"                       \
 132                   "mtspr %0, %1;"               \
 133                   : : "I" (CYGARC_REG_DC_CST), "r" (CYGARC_REG_DC_CMD_CD))
 134
 135 // Invalidate the entire cache
 136 // Note: Any locked lines will not be invalidated.
 137 #define HAL_DCACHE_INVALIDATE_ALL()                     \
 138     asm volatile ("sync;"                               \
 139                   "mtspr %0, %1;"                       \
 140                   : : "I" (CYGARC_REG_DC_CST),          \
 141                       "r" (CYGARC_REG_DC_CMD_IA))
 142
 143 // Synchronize the contents of the cache with memory.
 144 #if defined(CYGHWR_HAL_POWERPC_MPC8XX_850)
 145 // Note: the data cache flush seems to be broken on this chip :-(
 146 #define HAL_DCACHE_SYNC()                                       \
 147     CYG_MACRO_START                                             \
 148     cyg_int32 i;                                                \
 149     cyg_uint32 *__base = (cyg_uint32 *) (0);                    \
 150     for(i=0;i< (2 * HAL_DCACHE_SIZE/HAL_DCACHE_LINE_SIZE);i++,__base += HAL_DCACHE_LINE_SIZE/4){ \
 151         asm volatile ("lwz %%r0,0(%0);"::"r"(__base):"r0");     \
 152     }                                                           \
 153     CYG_MACRO_END
 154 #else
 155 #define HAL_DCACHE_SYNC()                                                     \
 156     CYG_MACRO_START                                                           \
 157     cyg_int32 i;                                                              \
 158     for (i = 0; i < HAL_DCACHE_SETS; i++){                                    \
 159         asm volatile ("sync;"                                                 \
 160                       "mtspr %0, %2;"                                         \
 161                       "mtspr %1, %4;"                                         \
 162                       "mtspr %0, %3;"                                         \
 163                       "mtspr %1, %4;"                                         \
 164                       : /* no output */                                       \
 165                       : /* %0 */ "I" (CYGARC_REG_DC_ADR),                     \
 166                         /* %1 */ "I" (CYGARC_REG_DC_CST),                     \
 167                         /* %2 */ "r" (CYGARC_REG_DC_ADR_WAY0                  \
 168                                       |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
 169                         /* %3 */ "r" (CYGARC_REG_DC_ADR_WAY1                  \
 170                                       |(i << CYGARC_REG_DC_ADR_SETID_SHIFT)), \
 171                         /* %4 */ "r" (CYGARC_REG_DC_CMD_FL));                 \
 172     }                                                                         \
 173     CYG_MACRO_END
 174 #endif
 175
 176 // Query the state of the data cache
 177 #define HAL_DCACHE_IS_ENABLED(_state_)                          \
 178     asm volatile ("mfspr  %0, %1;"                              \
 179                   "rlwinm %0,%0,1,31,31;"                       \
 180                   : "=r" (_state_) : "I" (CYGARC_REG_DC_CST))
 181
 182 // Set the data cache refill burst size
 183 //#define HAL_DCACHE_BURST_SIZE(_size_)
 184
 185 // Set the data cache write mode
 186 #define HAL_DCACHE_WRITE_MODE( _mode_ )                 \
 187     CYG_MACRO_START                                     \
 188     if (_mode_ == HAL_DCACHE_WRITETHRU_MODE) {          \
 189         asm volatile ("sync;"                           \
 190                   "mtspr %0, %1;"                       \
 191                   : : "I" (CYGARC_REG_DC_CST),          \
 192                       "r" (CYGARC_REG_DC_CMD_SW));      \
 193     }                                                   \
 194     if (_mode_ == HAL_DCACHE_WRITEBACK_MODE) {          \
 195         asm volatile ("sync;"                           \
 196                   "mtspr %0, %1;"                       \
 197                   : : "I" (CYGARC_REG_DC_CST),          \
 198                       "r" (CYGARC_REG_DC_CMD_CW));      \
 199     }                                                   \
 200     CYG_MACRO_END
 201
 202 #define HAL_DCACHE_WRITETHRU_MODE       0
 203 #define HAL_DCACHE_WRITEBACK_MODE       1
 204
 205
 206 // Load the contents of the given address range into the data cache
 207 // and then lock the cache so that it stays there.
 208
 209 // Restrictions: This implementation only allows a single area to be
 210 // locked at any one time. This area must be 2kB or less in size.
 211
 212 // Implementation: Flush entire cache, then invalidate it. This
 213 // ensures that the fetched data go into way0.
 214
 215 #define HAL_DCACHE_LOCK(_base_, _size_)                                       \
 216     CYG_MACRO_START                                                           \
 217     cyg_int32 __scratch;                                                      \
 218     cyg_uint32 __base = (cyg_uint32)(_base_);                                 \
 219     cyg_int32 __l = ((__base / HAL_DCACHE_LINE_SIZE) % HAL_DCACHE_SETS);      \
 220     cyg_int32 __count = ((_size_) / HAL_DCACHE_LINE_SIZE);                    \
 221     HAL_DCACHE_DISABLE();                                                     \
 222     HAL_DCACHE_SYNC ();                                                       \
 223     HAL_DCACHE_INVALIDATE_ALL ();                                             \
 224     HAL_DCACHE_ENABLE();                                                      \
 225     do {                                                                      \
 226         asm volatile ("lbz   %0,0(%1);"                                       \
 227                       "sync;"                                                 \
 228                       "mtspr %2, %4;"                                         \
 229                       "mtspr %3, %5;"                                         \
 230                       : /* %0 */ "=&r" (__scratch)                            \
 231                       : /* %1 */ "b" (__base),                                \
 232                         /* %2 */ "I" (CYGARC_REG_DC_ADR),                     \
 233                         /* %3 */ "I" (CYGARC_REG_DC_CST),                     \
 234                         /* %4 */ "r" (CYGARC_REG_DC_ADR_WAY0                  \
 235                                       |(__l<<CYGARC_REG_DC_ADR_SETID_SHIFT)), \
 236                         /* %5 */ "r" (CYGARC_REG_DC_CMD_LL));                 \
 237         __l++;                                                                \
 238         __base += HAL_DCACHE_LINE_SIZE;                                       \
 239     } while (__count--);                                                      \
 240     CYG_MACRO_END
 241
 242
 243 // Undo a previous lock operation
 244
 245 // Implementation: Unlocks entire cache.
 246
 247 #define HAL_DCACHE_UNLOCK(_base_, _size_)               \
 248     HAL_DCACHE_UNLOCK_ALL()
 249
 250
 251 // Unlock entire cache
 252 #define HAL_DCACHE_UNLOCK_ALL()                         \
 253     CYG_MACRO_START                                     \
 254     asm volatile ("sync;"                               \
 255                   "mtspr %0, %1;"                       \
 256                   : : "I" (CYGARC_REG_DC_CST),          \
 257                       "r" (CYGARC_REG_DC_CMD_UA));      \
 258     CYG_MACRO_END
 259
 260
 261
 262 //-----------------------------------------------------------------------------
 263 // Data cache line control
 264
 265 // Allocate cache lines for the given address range without reading its
 266 // contents from memory.
 267 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
 268
 269 // Write dirty cache lines to memory and invalidate the cache entries
 270 // for the given address range.
 271 #define HAL_DCACHE_FLUSH( _base_ , _size_ )                     \
 272     CYG_MACRO_START                                             \
 273     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 274     cyg_int32 __size = (cyg_int32) (_size_);                    \
 275     while (__size > 0) {                                        \
 276         asm volatile ("dcbf 0,%0;sync;" : : "r" (__base));      \
 277         __base += HAL_DCACHE_LINE_SIZE;                         \
 278         __size -= HAL_DCACHE_LINE_SIZE;                         \
 279     }                                                           \
 280     CYG_MACRO_END
 281
 282 // Invalidate cache lines in the given range without writing to memory.
 283 #define HAL_DCACHE_INVALIDATE( _base_ , _size_ )                \
 284     CYG_MACRO_START                                             \
 285     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 286     cyg_int32 __size = (cyg_int32) (_size_);                    \
 287     while (__size > 0) {                                        \
 288         asm volatile ("dcbi 0,%0;sync;" : : "r" (__base));      \
 289         __base += HAL_DCACHE_LINE_SIZE;                         \
 290         __size -= HAL_DCACHE_LINE_SIZE;                         \
 291     }                                                           \
 292     CYG_MACRO_END
 293
 294 // Write dirty cache lines to memory for the given address range.
 295 #define HAL_DCACHE_STORE( _base_ , _size_ )                     \
 296     CYG_MACRO_START                                             \
 297     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 298     cyg_int32 __size = (cyg_int32) (_size_);                    \
 299     while (__size > 0) {                                        \
 300         asm volatile ("dcbst 0,%0;sync;" : : "r" (__base));     \
 301         __base += HAL_DCACHE_LINE_SIZE;                         \
 302         __size -= HAL_DCACHE_LINE_SIZE;                         \
 303     }                                                           \
 304     CYG_MACRO_END
 305
 306 // Preread the given range into the cache with the intention of reading
 307 // from it later.
 308 #define HAL_DCACHE_READ_HINT( _base_ , _size_ )                 \
 309     CYG_MACRO_START                                             \
 310     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 311     cyg_int32 __size = (cyg_int32) (_size_);                    \
 312     while (__size > 0) {                                        \
 313         asm volatile ("dcbt 0,%0;" : : "r" (__base));           \
 314         __base += HAL_DCACHE_LINE_SIZE;                         \
 315         __size -= HAL_DCACHE_LINE_SIZE;                         \
 316     }                                                           \
 317     CYG_MACRO_END
 318
 319 // Preread the given range into the cache with the intention of writing
 320 // to it later.
 321 #define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )                \
 322     CYG_MACRO_START                                             \
 323     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 324     cyg_int32 __size = (cyg_int32) (_size_);                    \
 325     while (__size > 0) {                                        \
 326         asm volatile ("dcbtst 0,%0;" : : "r" (__base));         \
 327         __base += HAL_DCACHE_LINE_SIZE;                         \
 328         __size -= HAL_DCACHE_LINE_SIZE;                         \
 329     }                                                           \
 330     CYG_MACRO_END
 331
 332 // Allocate and zero the cache lines associated with the given range.
 333 #define HAL_DCACHE_ZERO( _base_ , _size_ )                      \
 334     CYG_MACRO_START                                             \
 335     cyg_uint32 __base = (cyg_uint32) (_base_);                  \
 336     cyg_int32 __size = (cyg_int32) (_size_);                    \
 337     while (__size > 0) {                                        \
 338         asm volatile ("dcbz 0,%0;" : : "r" (__base));           \
 339         __base += HAL_DCACHE_LINE_SIZE;                         \
 340         __size -= HAL_DCACHE_LINE_SIZE;                         \
 341     }                                                           \
 342     CYG_MACRO_END
 343
 344 //-----------------------------------------------------------------------------
 345 // Global control of Instruction cache
 346
 347 // Enable the instruction cache
 348 #define HAL_ICACHE_ENABLE()                     \
 349     asm volatile ("isync;"                      \
 350                   "mtspr %0, %1;"               \
 351                   "isync"                       \
 352                   : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CE))
 353
 354 // Disable the instruction cache
 355 #define HAL_ICACHE_DISABLE()                    \
 356     asm volatile ("isync;"                      \
 357                   "mtspr %0, %1;"               \
 358                   "isync"                       \
 359                   : : "I" (CYGARC_REG_IC_CST), "r" (CYGARC_REG_IC_CMD_CD))
 360
 361 // Invalidate the entire cache
 362 #define HAL_ICACHE_INVALIDATE_ALL()                     \
 363     asm volatile ("isync;"                              \
 364                   "mtspr %0, %1;"                       \
 365                   "isync"                               \
 366                   : : "I" (CYGARC_REG_IC_CST),          \
 367                       "r" (CYGARC_REG_IC_CMD_IA))
 368
 369 // Synchronize the contents of the cache with memory.
 370 #define HAL_ICACHE_SYNC()                               \
 371     HAL_ICACHE_INVALIDATE_ALL()
 372
 373 // Query the state of the instruction cache
 374 #define HAL_ICACHE_IS_ENABLED(_state_)                          \
 375     asm volatile ("mfspr  %0, %1;"                              \
 376                   "rlwinm %0,%0,1,31,31;"                       \
 377                   : "=r" (_state_) : "I" (CYGARC_REG_IC_CST))
 378
 379 // Set the instruction cache refill burst size
 380 //#define HAL_ICACHE_BURST_SIZE(_size_)
 381
 382
 383 // Load the contents of the given address range into the instruction cache
 384 // and then lock the cache so that it stays there.
 385
 386 // Restrictions: This implementation only allows a single area to be
 387 // locked at any one time. This area must be 2kB or less in size.
 388
 389 // Implementation: Flush entire cache, then invalidate it. This
 390 // ensures that the fetched data go into way0.
 391
 392 #define HAL_ICACHE_LOCK(_base_, _size_)                                       \
 393     CYG_MACRO_START                                                           \
 394     unsigned long __base =                                                    \
 395         ((unsigned long) (_base_)) & ~(HAL_ICACHE_LINE_SIZE-1);               \
 396     int __count = ((_size_) / HAL_ICACHE_LINE_SIZE);                          \
 397     do {                                                                      \
 398         asm volatile ("mtspr %0, %2;"                                         \
 399                       "mtspr %1, %3;"                                         \
 400                       "isync;"                                                \
 401                       : /* no output */                                       \
 402                       : /* %0 */ "I" (CYGARC_REG_IC_ADR),                     \
 403                         /* %1 */ "I" (CYGARC_REG_IC_CST),                     \
 404                         /* %2 */ "r" (__base),                                \
 405                         /* %3 */ "r" (CYGARC_REG_IC_CMD_LL));                 \
 406         __base += HAL_ICACHE_LINE_SIZE;                                       \
 407     } while (__count--);                                                      \
 408     CYG_MACRO_END
 409
 410 // Undo a previous lock operation
 411
 412 // Implementation: Unlocks entire cache.
 413 #define HAL_ICACHE_UNLOCK(_base_, _size_)       \
 414     HAL_ICACHE_UNLOCK_ALL()
 415
 416 // Unlock entire cache
 417 #define HAL_ICACHE_UNLOCK_ALL()                         \
 418     CYG_MACRO_START                                     \
 419     asm volatile ("sync;"                               \
 420                   "mtspr %0, %1;"                       \
 421                   : : "I" (CYGARC_REG_IC_CST),          \
 422                       "r" (CYGARC_REG_IC_CMD_UA));      \
 423     CYG_MACRO_END
 424
 425 //-----------------------------------------------------------------------------
 426 // Instruction cache line control
 427
 428 // Invalidate cache lines in the given range without writing to memory.
 429 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
 430
 431 //-----------------------------------------------------------------------------
 432 #endif // ifndef CYGONCE_VAR_CACHE_H
 433 // End of var_cache.h