1 //=============================================================================
5 // HAL auxiliary objects and code; per platform
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
10 // This file is part of eCos, the Embedded Configurable Operating System.
11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
12 // Copyright (C) 2002 Gary Thomas
14 // eCos is free software; you can redistribute it and/or modify it under
15 // the terms of the GNU General Public License as published by the Free
16 // Software Foundation; either version 2 or (at your option) any later version.
18 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
19 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
23 // You should have received a copy of the GNU General Public License along
24 // with eCos; if not, write to the Free Software Foundation, Inc.,
25 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
27 // As a special exception, if other files instantiate templates or use macros
28 // or inline functions from this file, or you compile this file and link it
29 // with other works to produce a work based on this file, this file does not
30 // by itself cause the resulting work to be covered by the GNU General Public
31 // License. However the source code for this file must still be made available
32 // in accordance with section (3) of the GNU General Public License.
34 // This exception does not invalidate any other reasons why a work based on
35 // this file might be covered by the GNU General Public License.
37 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
38 // at http://sources.redhat.com/ecos/ecos-license/
39 // -------------------------------------------
40 //####ECOSGPLCOPYRIGHTEND####
41 //=============================================================================
42 //#####DESCRIPTIONBEGIN####
47 // Purpose: HAL aux objects: startup tables.
48 // Description: Tables for per-platform initialization
50 //####DESCRIPTIONEND####
52 //=============================================================================
54 #include <pkgconf/hal.h>
55 #include <cyg/hal/hal_mem.h> // HAL memory definitions
56 #include <cyg/infra/cyg_type.h>
57 #include <cyg/hal/hal_if.h> // hal_if_init
58 #include <cyg/hal/hal_io.h> // hal_if_init
59 #include <cyg/hal/hal_misc.h> // cyg_hal_is_break
61 #include <cyg/hal/drv_api.h> // CYG_ISR_HANDLED
62 #include <cyg/hal/hal_diag.h>
63 #include <cyg/hal/ppc_regs.h>
64 #include <cyg/hal/hal_intr.h>
65 #include <cyg/hal/mpc8260.h> // Needed for IMMR structure
67 #ifdef CYG_HAL_STARTUP_ROM
69 #include <pkgconf/redboot.h>
71 // Exported CLI function
72 RedBoot_cmd("sdram_test",
79 do_sdram_test(int argc, char *argv[])
81 unsigned long oldints;
83 diag_printf("Starting test for SDRAM.\n");
84 diag_printf("D18 will indicate PASS/FAIL (Green/Red).\n");
85 diag_printf("Resetting board will be necessary after test completion.\n");
86 HAL_DISABLE_INTERRUPTS(oldints);
91 // For Baud Rate Calculation, see MPC8260 PowerQUICC II User's Manual
92 // 16.3 UART Baud Rate Examples, page 16-5.
93 #define UART_BIT_RATE(n) \
94 (((int)(CYGHWR_HAL_POWERPC_BOARD_SPEED*1000000))/(n * 64))
95 #define UART_BAUD_RATE CYGNUM_HAL_TS6_DIAG_BAUD
97 // The memory map is weakly defined, allowing the application to redefine
98 // it if necessary. The regions defined below are the minimum requirements.
99 CYGARC_MEMDESC_TABLE CYGBLD_ATTRIB_WEAK = {
100 // Mapping for the Motorola MPC8260 development board
101 CYGARC_MEMDESC_CACHE( 0x00000000, 0x04000000 ), // Main memory 60x SDRAM
102 // Mapping for the FPGA and the MPC8260 Internal memory
103 CYGARC_MEMDESC_NOCACHE( 0x04500000, 0x00400000 ),
104 // Mapping for the Cluster Bus
105 CYGARC_MEMDESC_NOCACHE( 0xE0000000, 0x10000000 ),
106 // Mapping for the FLASH
107 CYGARC_MEMDESC_NOCACHE( 0xff800000, 0x00800000 ), // ROM region
109 CYGARC_MEMDESC_TABLE_END
113 /***********************/
114 /* Global Declarations */
115 /***********************/
118 volatile t_PQ2IMM *IMM; /* IMM base pointer */
120 //--------------------------------------------------------------------------
121 // Platform init code.
123 hal_platform_init(void)
126 // Ports and Pins assigned for General Purpose I/O
127 // PORT PIN(s) DIR (I/O) Name Init Value Comment
128 //-------------------------------------------------------------------
129 // A 30-31 TBD TBD Wires to RF Board
130 // A 29 O TS_RESET_L 0 Tiger Sharc Reset
131 // A 28 O LP_ENB_L 1 Link Port Buffer Enable
132 // A 26-27 TBD TBD Wires to RF Board
133 // A 18-23 TBD TBD Wires to each Tiger Sharc
134 // A 12-17 O xxxxxxxxxx 0 Tiger Sharc Interrupt
135 // B 4-7 O xxxxxxxxxx TBD User controlled LEDs
136 // C 8 I xxxxxxxxxx xxx RF Board Interrupt
137 // C 6 I xxxxxxxxxx xxx FPGA Interrupt
138 // C 0-5 I xxxxxxxxxx xxx TSn Interrupt
139 // D 20 ? PPC_WAIT TBD Open Drain == High Z
140 // D 7-9 O CIMP 0-2 110 TS Impedance ctrl
141 // D 4-6 O DS 0-2 100 TS Drive Strength
144 // Ports and Pins assigned for Dedicated Pin Assignment
145 // PORT PIN(s) DIR (I/O) Name Init Value Comment
146 //-------------------------------------------------------------------
147 // D 16-19 x TBD SPI to RF Board
152 #define TS6_PPARA_INIT_MASK 0xFFF00000
153 #define TS6_PDIRA_INIT_MASK 0x3003F000
154 #define TS6_PDATA_INIT_MASK 0x1003F000
155 IMM = (t_PQ2IMM *)0x04700000; /* MPC8260 internal register map */
157 /*-------------------------------------------*/
158 /* Program the Port Pin Registers */
159 /*-------------------------------------------*/
161 IMM->io_regs[PORT_A].ppar &= 0xFFF00000; /* Clear bits for GPIO */
162 IMM->io_regs[PORT_A].pdir |= 0x000FC00C; /* Set bits on outputs */
163 IMM->io_regs[PORT_A].pdat |= 0x00000008; /* Set high outputs bits */
164 IMM->io_regs[PORT_A].pdat &= 0xFFF03FFB; /* Clear low output bits */
166 // Initialize Port B Pins 4,5,6,7 general purpose IO
167 // Pin == 0 ==> LED on
169 // Pin 5 LED 18, Green
171 // Pin 7 LED 17, Green
172 IMM->io_regs[PORT_B].ppar &= 0xF0FFFFFF; /* Clear 4-7 */
173 IMM->io_regs[PORT_B].pdir |= 0x0F000000; /* Set 4-7 as outputs */
174 IMM->io_regs[PORT_B].pdat |= 0x0F000000; /* Clear LED's */
175 IMM->io_regs[PORT_B].pdat &= 0xFDFFFFFF; /* Set LED's 17 to green */
177 IMM->io_regs[PORT_C].ppar &= 0x007FFFFF; /* Clear 0 -8 */
178 IMM->io_regs[PORT_C].pdir &= 0x007FFFFF; /* Configure as inputs */
179 //IMM->io_regs[PORT_C].podr &= 0xFF800000; /* Configure as inputs */
181 IMM->io_regs[PORT_D].ppar &= 0xF03FF7FF;
182 IMM->io_regs[PORT_D].pdir |= 0x0FC00000;
183 IMM->io_regs[PORT_D].podr |= 0x00000800;
184 IMM->io_regs[PORT_D].pdat |= 0x09800000;
186 #ifdef USE_CPM_SPI_CONTROLLER
187 // Dedicated Pin assignments for SPI
188 IMM->io_regs[PORT_D].ppar |= 0x0000F000;
189 IMM->io_regs[PORT_D].podr &= 0xFFFF0FFF;
190 IMM->io_regs[PORT_D].pdir |= 0x0000F000;
192 // The ts6 board does not use the SPI controller provided by the CPM,
193 // instead it is left up to the application to control the SPI.
194 // Therefore, initialize the SPI specific pins as General Purpose I/O
195 // and Bi-directional.
196 IMM->io_regs[PORT_D].ppar &= 0xFFFF0FFF; /* General Purpose I/O */
197 IMM->io_regs[PORT_D].pdir &= 0xFFFF0FFF; /* input or Bi-directional */
200 #ifdef CYGSEM_HAL_VIRTUAL_VECTOR_SUPPORT