1 #ifndef CYGONCE_HAL_INTR_VECS_H
2 #define CYGONCE_HAL_INTR_VECS_H
4 //==========================================================================
8 // HAL Interrupt support for variants with vectored style
9 // exception/interrupt mapping (SH1/SH2)
11 //==========================================================================
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44 //==========================================================================
45 //#####DESCRIPTIONBEGIN####
48 // Contributors: jskov
50 // Purpose: Define Interrupt support
51 // Description: The macros defined here provide the HAL APIs for handling
54 // Usage: Is included from <cyg/hal/hal_intr.h>
56 //####DESCRIPTIONEND####
58 //==========================================================================
60 //--------------------------------------------------------------------------
61 // SH exception vectors. These correspond to VSRs and are the values
62 // to use for HAL_VSR_GET/SET
64 // Note that exceptions are decoded - there is a VSR slot for each exception
65 // source, while interrupts are handled via the same VSR.
67 // The SH2 vectors are set up to provide exception/interrupt behavior
68 // much like that found in the SH3/SH4 CPUs. See hal_var_sp.inc for
69 // implementation details.
71 // While there are 256 vectors, we only reserve space for 64 VSRs.
72 // With TRAPs and Interrupts wired to VSRs 32+33, there's still plenty
73 // of free VSRs for use by the application.
75 #define CYGNUM_HAL_VECTOR_POWERON 0 // power-on
77 #define CYGNUM_HAL_VECTOR_RESET 2 // reset
79 #define CYGNUM_HAL_VECTOR_ILLEGAL_INSTRUCTION 4 // reserved instruction
81 #define CYGNUM_HAL_VECTOR_ILLEGAL_SLOT_INSTRUCTION 6
82 // illegal instruction in delay slot
84 #define CYGNUM_HAL_VECTOR_CPU_ADDRESS_ERROR 9 // CPU address error
85 #define CYGNUM_HAL_VECTOR_DMA_ADDRESS_ERROR 10 // DMA address error
86 //#define CYGNUM_HAL_VECTOR_NMI 11 // This gets mapped as irq 0
87 #define CYGNUM_HAL_VECTOR_USER_BREAK 12 // user breakpoint
88 #define CYGNUM_HAL_VECTOR_H_UDI 13 // H-UDI
90 #define CYGNUM_HAL_VECTOR_TRAP 32 // user breakpoint
91 #define CYGNUM_HAL_VECTOR_INTERRUPT 33 // all interrupts
93 #ifndef CYG_VECTOR_IS_INTERRUPT
94 # define CYG_VECTOR_IS_INTERRUPT(v) (CYGNUM_HAL_VECTOR_INTERRUPT == (v))
97 #define CYGNUM_HAL_VSR_MIN CYGNUM_HAL_VECTOR_POWERON
98 #ifndef CYGNUM_HAL_VSR_MAX
99 # define CYGNUM_HAL_VSR_MAX 63
101 #define CYGNUM_HAL_VSR_COUNT ( CYGNUM_HAL_VSR_MAX + 1 )
103 #ifndef CYGNUM_HAL_VSR_EXCEPTION_COUNT
104 # define CYGNUM_HAL_VSR_EXCEPTION_COUNT (CYGNUM_HAL_VECTOR_TRAP-CYGNUM_HAL_VECTOR_POWERON+1)
107 // The decoded interrupts.
108 #define CYGNUM_HAL_INTERRUPT_NMI 0
109 // These are equivalent to HW_EXC vectors 64 and up
110 #define CYGNUM_HAL_INTERRUPT_HW_EXC_BASE 64
111 #define CYGNUM_HAL_INTERRUPT_LVL0 1 // note that LVLx and IRQx share vectors!
112 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ0 1
113 #define CYGNUM_HAL_INTERRUPT_LVL1 2
114 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ1 2
115 #define CYGNUM_HAL_INTERRUPT_LVL2 3
116 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ2 3
117 #define CYGNUM_HAL_INTERRUPT_LVL3 4
118 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ3 4
119 #define CYGNUM_HAL_INTERRUPT_LVL4 5
120 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ4 5
121 #define CYGNUM_HAL_INTERRUPT_LVL5 6
122 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ5 6
123 #define CYGNUM_HAL_INTERRUPT_LVL6 7
124 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ6 7
125 #define CYGNUM_HAL_INTERRUPT_LVL7 8
126 #define CYGNUM_HAL_INTERRUPT_IRQ_IRQ7 8
128 #ifndef CYGNUM_HAL_INTERRUPT_LVL_MAX
129 # define CYGNUM_HAL_INTERRUPT_LVL_MAX CYGNUM_HAL_INTERRUPT_LVL7
132 #ifndef CYGNUM_HAL_ISR_MAX
133 # define CYGNUM_HAL_ISR_MAX CYGNUM_HAL_INTERRUPT_IRQ_IRQ7
136 #define CYGNUM_HAL_ISR_MIN CYGNUM_HAL_INTERRUPT_NMI
137 #define CYGNUM_HAL_ISR_COUNT ( CYGNUM_HAL_ISR_MAX - CYGNUM_HAL_ISR_MIN + 1 )
139 //--------------------------------------------------------------------------
140 // Exception vectors. These are the values used when passed out to an
141 // external exception handler using cyg_hal_deliver_exception()
143 // The exception indexes are given by the HW_EXC vectors. Variants may define additional
144 // exception vectors.
146 #define CYGNUM_HAL_EXCEPTION_POWERON 0 // power-on
147 #define CYGNUM_HAL_EXCEPTION_RESET 2 // reset
148 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_INSTRUCTION 4 // illegal instruction
149 #define CYGNUM_HAL_EXCEPTION_ILLEGAL_SLOT_INSTRUCTION 6 // illegal instruction in the slot
150 #define CYGNUM_HAL_EXCEPTION_DATA_ACCESS 9 // CPU address error
151 #define CYGNUM_HAL_EXCEPTION_DMA_DATA_ACCESS 10 // DMA address error
152 #define CYGNUM_HAL_EXCEPTION_USER_BREAK 12 // user break
153 #define CYGNUM_HAL_EXCEPTION_H_UDI 13 // H-UDI
154 #define CYGNUM_HAL_EXCEPTION_TRAP 32 // unconditional trap
156 #define CYGNUM_HAL_EXCEPTION_MIN CYGNUM_HAL_EXCEPTION_POWERON
158 #ifndef CYGNUM_HAL_EXCEPTION_MAX
159 # define CYGNUM_HAL_EXCEPTION_MAX CYGNUM_HAL_EXCEPTION_TRAP
162 #define CYGNUM_HAL_EXCEPTION_COUNT \
163 ( CYGNUM_HAL_EXCEPTION_MAX - CYGNUM_HAL_EXCEPTION_MIN + 1 )
165 // For the stub exception handling
166 #define _CYGNUM_HAL_VECTOR_FIRST_MEM_FAULT CYGNUM_HAL_EXCEPTION_DATA_ACCESS
167 #define _CYGNUM_HAL_VECTOR_LAST_MEM_FAULT CYGNUM_HAL_EXCEPTION_DMA_DATA_ACCESS
169 #ifndef __ASSEMBLER__
171 #include <cyg/infra/cyg_type.h>
173 externC void hal_delay_us(int);
174 #define HAL_DELAY_US(n) hal_delay_us(n)
176 #endif // __ASSEMBLER__
178 //--------------------------------------------------------------------------
179 #endif // ifndef CYGONCE_HAL_INTR_VECS_H
180 // End of hal_intr_vecs.h