1 #ifndef CYGONCE_HAL_VAR_BANK_H
2 #define CYGONCE_HAL_VAR_BANK_H
3 //=============================================================================
7 // Architecture abstractions for variants without banked registers
9 //=============================================================================
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42 //=============================================================================
43 //#####DESCRIPTIONBEGIN####
48 // Purpose: Architecture abstractions for variants without banked registers
50 //####DESCRIPTIONEND####
52 //=============================================================================
54 //-----------------------------------------------------------------------------
55 // Processor saved states:
59 // These are common to all saved states
60 cyg_uint32 r[16]; // Data regs
61 cyg_uint32 macl; // Multiply and accumulate - low
62 cyg_uint32 mach; // Multiply and accumulate - high
63 cyg_uint32 pr; // Procedure Reg
64 #if 0 // FIXME: how are these accessed?
65 cyg_uint32 mod; // Modulo register
66 cyg_uint32 rs; // Repeat start
67 cyg_uint32 re; // Repeat end
69 cyg_uint32 sr; // Status Reg
70 cyg_uint32 pc; // Program Counter
72 // This marks the limit of state saved during a context switch and
73 // is used to calculate necessary stack allocation for context switches.
74 // It would probably be better to have a union instead...
75 cyg_uint32 context_size[0];
77 // These are only saved on interrupts
78 cyg_uint32 vbr; // Vector Base Register
79 cyg_uint32 gbr; // Global Base Register
81 // These are only saved on interrupts
82 cyg_uint32 event; // vector number
85 //-----------------------------------------------------------------------------
86 // Context Initialization
87 // Initialize the context of a thread.
89 // _sparg_ name of variable containing current sp, will be written with new sp
90 // _thread_ thread object address, passed as argument to entry point
91 // _entry_ entry point address.
92 // _id_ bit pattern used in initializing registers, for debugging.
94 #define HAL_THREAD_INIT_CONTEXT( _sparg_, _thread_, _entry_, _id_ ) \
96 register CYG_WORD _sp_ = (CYG_WORD)_sparg_; \
97 register HAL_SavedRegisters *_regs_; \
99 _sp_ = _sp_ & ~(CYGARC_ALIGNMENT-1); \
100 /* Note that _regs_ below should be aligned if HAL_SavedRegisters */ \
101 /* stops being aligned to CYGARC_ALIGNMENT */ \
102 _regs_ = (HAL_SavedRegisters *)((_sp_) - sizeof(HAL_SavedRegisters)); \
103 for( _i_ = 0; _i_ < 16; _i_++ ) (_regs_)->r[_i_] = (_id_)|_i_; \
104 (_regs_)->r[15] = (CYG_WORD)(_regs_); /* SP = top of stack */ \
105 (_regs_)->r[04] = (CYG_WORD)(_thread_); /* R4 = arg1 = thread ptr */ \
106 (_regs_)->mach = 0; /* MACH = 0 */ \
107 (_regs_)->macl = 0; /* MACL = 0 */ \
108 (_regs_)->pr = (CYG_WORD)(_entry_); /* PR = entry point */ \
109 (_regs_)->sr = 0; /* SR = enable interrupts */ \
110 (_regs_)->pc = (CYG_WORD)(_entry_); /* set PC for thread dbg */ \
111 _sparg_ = (CYG_ADDRESS)_regs_; \
114 //-----------------------------------------------------------------------------
115 // Thread register state manipulation for GDB support.
117 // Translate a stack pointer as saved by the thread context macros above into
118 // a pointer to a HAL_SavedRegisters structure.
119 #define HAL_THREAD_GET_SAVED_REGISTERS( _sp_, _regs_ ) \
120 (_regs_) = (HAL_SavedRegisters *)(_sp_)
122 // Copy a set of registers from a HAL_SavedRegisters structure into a
123 // GDB ordered array.
124 #define HAL_GET_GDB_REGISTERS( _aregval_, _regs_ ) \
126 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
129 for( _i_ = 0; _i_ < 16; _i_++ ) \
130 _regval_[_i_] = (_regs_)->r[_i_]; \
132 _regval_[16] = (_regs_)->pc; \
133 _regval_[17] = (_regs_)->pr; \
134 _regval_[18] = (_regs_)->gbr; \
135 _regval_[19] = (_regs_)->vbr; \
136 _regval_[20] = (_regs_)->mach; \
137 _regval_[21] = (_regs_)->macl; \
138 _regval_[22] = (_regs_)->sr; \
140 /* 23-51 not used atm. */ \
143 // Copy a GDB ordered array into a HAL_SavedRegisters structure.
144 #define HAL_SET_GDB_REGISTERS( _regs_ , _aregval_ ) \
146 CYG_ADDRWORD *_regval_ = (CYG_ADDRWORD *)(_aregval_); \
149 for( _i_ = 0; _i_ < 16; _i_++ ) \
150 (_regs_)->r[_i_] = _regval_[_i_]; \
152 (_regs_)->pc = _regval_[16]; \
153 (_regs_)->pr = _regval_[17]; \
154 (_regs_)->gbr = _regval_[18]; \
155 (_regs_)->vbr = _regval_[19]; \
156 (_regs_)->mach = _regval_[20]; \
157 (_regs_)->macl = _regval_[21]; \
158 (_regs_)->sr = _regval_[22]; \
161 //--------------------------------------------------------------------------
162 // CPU address space translation macros
163 #define CYGARC_BUS_ADDRESS(x) ((CYG_ADDRWORD)(x) & 0x1fffffff)
164 #define CYGARC_CACHED_ADDRESS(x) (CYGARC_BUS_ADDRESS(x)|0x00000000)
165 #define CYGARC_UNCACHED_ADDRESS(x) (CYGARC_BUS_ADDRESS(x)|0x20000000)
167 //-----------------------------------------------------------------------------
168 #endif // CYGONCE_HAL_VAR_BANK_H
169 // End of hal_var_bank.h