1 ##=============================================================================
5 ## EDK board hardware setup
7 ##=============================================================================
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40 ##=============================================================================
41 #######DESCRIPTIONBEGIN####
46 ## Purpose: EDK7708 board hardware setup
47 ## Description: This file contains any code needed to initialize the
48 ## hardware on a Hitachi SH3 EDK7708 board.
50 ######DESCRIPTIONEND####
52 ##=============================================================================
54 #include <pkgconf/hal.h>
55 #include <cyg/hal/sh_regs.h>
57 .globl _hal_hardware_init
60 // Set up the Bus State Controller
61 mov.l $BSC_settings_table,r3
62 1: mov.w @r3+,r0 // Address (or zero)
67 mov.w r1,@r0 // delay slot
75 .long BSC_settings_table
77 # These are the settings set by the Hitachi ROM Monitor.
79 # BCR2: Bus size of areas 1-6 to 32 bits
82 # BCR1: Areas 2 and 3 are SDRAM
85 # BCR2: Bus size of areas 1-6 to 32 bits [note: second write!]
88 # WCR1: 3 wait-state cycles inserted for all areas
91 # WCR2: extra wait states and full pitch for burst
94 # MCR: RAS/CAS & burst timing area 2/3
98 # DCR: RAS/CAS & burst timing area 2
101 # PCR: PCMCIA disabled
105 # RTCNT: refresh counter (needs a5 in top byte to accept write)
106 .word CYGARC_REG_RTCNT
107 .word (0xa500 | 0x0000)
108 # RTCOR: refresh time constant (needs a5 in top byte to accept write)
109 .word CYGARC_REG_RTCOR
110 .word (0xa500 | 0x003b)
111 # RFCR: refresh count register (needs a4 in top byte to accept write)
112 .word CYGARC_REG_RFCR
113 .word (0xa400 | 0x0000)
114 # RTCSR: refresh timer control (needs a5 in top byte to accept write)
115 .word CYGARC_REG_RTCSR
116 .word (0xa500 | 0x0008)
125 #------------------------------------------------------------------------------