1 #ifndef CYGONCE_HAL_PLATFORM_INC
2 #define CYGONCE_HAL_PLATFORM_INC
3 ##=============================================================================
7 ## Hitachi SE7751 board assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
12 ## This file is part of eCos, the Embedded Configurable Operating System.
13 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
15 ## eCos is free software; you can redistribute it and/or modify it under
16 ## the terms of the GNU General Public License as published by the Free
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19 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
20 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
21 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
24 ## You should have received a copy of the GNU General Public License along
25 ## with eCos; if not, write to the Free Software Foundation, Inc.,
26 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
28 ## As a special exception, if other files instantiate templates or use macros
29 ## or inline functions from this file, or you compile this file and link it
30 ## with other works to produce a work based on this file, this file does not
31 ## by itself cause the resulting work to be covered by the GNU General Public
32 ## License. However the source code for this file must still be made available
33 ## in accordance with section (3) of the GNU General Public License.
35 ## This exception does not invalidate any other reasons why a work based on
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39 ## at http://sources.redhat.com/ecos/ecos-license/
40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
48 ## Purpose: Hitachi SE7751 platform startup
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the Hitachi SE7751
53 ## #include <cyg/hal/platform.inc>
57 ######DESCRIPTIONEND####
59 ##=============================================================================
61 #include <pkgconf/hal.h>
63 #include <cyg/hal/sh_offsets.inc>
64 #include <cyg/hal/sh_regs.h>
66 #------------------------------------------------------------------------------
67 # Hardware initialization.
75 .macro hal_hardware_init
78 1: mov.l @r3+,r0 // Data type
79 cmp/eq #END,r0 // End of table
100 mov.l @r3+,r0 // addr
101 mov.l @r3+,r1 // data
107 mov.l @r3+,r0 // count
117 .long INT16, CYGARC_REG_WTCSR, 0xA502
118 .long INT16, CYGARC_REG_WTCNT, 0x5A00
119 .long INT16, CYGARC_REG_FRQCR, CYGARC_REG_FRQCR_INIT
120 .long INT32, CYGARC_REG_BCR1, 0x00080008
121 .long INT16, CYGARC_REG_BCR2, 0x2ffc
122 .long INT32, CYGARC_REG_WCR1, 0x02770771
123 .long INT32, CYGARC_REG_WCR2, 0x7ffe4fe7
124 .long INT32, CYGARC_REG_WCR3, 0x01777771
125 .long INT16, CYGARC_REG_PCR, 0x0000
126 .long INT16, CYGARC_REG_RTCNT, 0xa500
127 .long INT16, CYGARC_REG_RTCOR, 0xa506
128 .long INT16, CYGARC_REG_RFCR, 0xa400
129 .long INT32, CYGARC_REG_MCR, 0x100901b4
130 .long INT8, 0xff940088, 0x00 // CS3 area SDRAM mode register
131 .long INT16, CYGARC_REG_RTCSR, 0xa508
133 .long INT32, CYGARC_REG_MCR, 0x500901b4
134 .long INT8, 0xff940088, 0x00 // CS3 area SDRAM mode register
135 .long INT16, CYGARC_REG_RTCSR, 0xa518
136 .long INT32, CYGARC_REG_PCTRA, 0x00000000
137 .long INT32, CYGARC_REG_PCTRB, 0x00000000
138 .long INT16, CYGARC_REG_GPIOIC, 0x0000
143 #------------------------------------------------------------------------------
144 # Monitor initialization.
146 #ifndef CYGPKG_HAL_SH_MON_DEFINED
148 #if !defined(CYG_HAL_STARTUP_RAM) || \
149 ( defined(CYG_HAL_STARTUP_RAM) && \
150 !defined(CYGSEM_HAL_USE_ROM_MONITOR))
152 # If we are not starting up from RAM, or we are starting in
153 # RAM and NOT using a ROM monitor, initialize the VSR table.
156 mov.l $hal_vsr_table,r3
157 # Write exception vectors
158 mov.l $cyg_hal_default_exception_vsr,r4
159 mov #CYGNUM_HAL_VSR_EXCEPTION_COUNT,r5
164 # Write interrupt vector
165 mov.l $cyg_hal_default_interrupt_vsr,r4
166 mov.l $hal_vsr_table,r3
167 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
173 SYM_PTR_REF(cyg_hal_default_exception_vsr)
174 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
175 SYM_PTR_REF(hal_vsr_table)
179 #elif defined(CYG_HAL_STARTUP_RAM) && defined(CYGSEM_HAL_USE_ROM_MONITOR)
181 # Initialize the VSR table entries
182 # We only take control of the interrupt vector,
183 # the rest are left to the ROM for now...
186 # Write interrupt vector
187 mov.l $hal_vsr_table,r3
188 mov.l $cyg_hal_default_interrupt_vsr,r4
189 add #CYGNUM_HAL_VECTOR_INTERRUPT*4,r3
195 SYM_PTR_REF(cyg_hal_default_interrupt_vsr)
196 SYM_PTR_REF(hal_vsr_table)
208 #define CYGPKG_HAL_SH_MON_DEFINED
210 #endif // CYGPKG_HAL_SH_MON_DEFINED
212 #endif // CYGONCE_HAL_PLATFORM_INC