packages/hal/sh/se7751/v2_0/include/plf_io.h

   1 #ifndef CYGONCE_PLF_IO_H
   2 #define CYGONCE_PLF_IO_H
   3
   4 //=============================================================================
   5 //
   6 //      plf_io.h
   7 //
   8 //      Platform specific IO support
   9 //
  10 //=============================================================================
  11 //####ECOSGPLCOPYRIGHTBEGIN####
  12 // -------------------------------------------
  13 // This file is part of eCos, the Embedded Configurable Operating System.
  14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  15 //
  16 // eCos is free software; you can redistribute it and/or modify it under
  17 // the terms of the GNU General Public License as published by the Free
  18 // Software Foundation; either version 2 or (at your option) any later version.
  19 //
  20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  22 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  23 // for more details.
  24 //
  25 // You should have received a copy of the GNU General Public License along
  26 // with eCos; if not, write to the Free Software Foundation, Inc.,
  27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  28 //
  29 // As a special exception, if other files instantiate templates or use macros
  30 // or inline functions from this file, or you compile this file and link it
  31 // with other works to produce a work based on this file, this file does not
  32 // by itself cause the resulting work to be covered by the GNU General Public
  33 // License. However the source code for this file must still be made available
  34 // in accordance with section (3) of the GNU General Public License.
  35 //
  36 // This exception does not invalidate any other reasons why a work based on
  37 // this file might be covered by the GNU General Public License.
  38 //
  39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  40 // at http://sources.redhat.com/ecos/ecos-license/
  41 // -------------------------------------------
  42 //####ECOSGPLCOPYRIGHTEND####
  43 //=============================================================================
  44 //#####DESCRIPTIONBEGIN####
  45 //
  46 // Author(s):    jskov
  47 // Contributors: jskov
  48 // Date:         2001-07-10
  49 // Purpose:      SE7751 IO support macros
  50 // Description:
  51 // Usage:        #include <cyg/hal/plf_io.h>
  52 //
  53 //####DESCRIPTIONEND####
  54 //
  55 //=============================================================================
  56
  57 #include <cyg/hal/hal_intr.h>
  58 #include <cyg/hal/mod_regs_pcic.h>
  59
  60 //-----------------------------------------------------------------------------
  61 // PCI host setup details - map full 64MB in MEM1
  62 #define CYGARC_REG_PCIC_BAR0_PLF_INIT 0xab000001
  63 #define CYGARC_REG_PCIC_BAR1_PLF_INIT 0x0c000000
  64 #define CYGARC_REG_PCIC_BAR2_PLF_INIT 0xd0000000
  65 #define CYGARC_REG_PCIC_LSR0_PLF_INIT 0x03f00000
  66 #define CYGARC_REG_PCIC_LSR1_PLF_INIT 0x00000000
  67 #define CYGARC_REG_PCIC_LAR0_PLF_INIT 0x0c000000
  68 #define CYGARC_REG_PCIC_LAR1_PLF_INIT 0x00000000
  69
  70
  71 extern cyg_uint32 cyg_hal_sh_pcic_pci_cfg_read_dword (cyg_uint32 bus, cyg_uint32 devfn,
  72                                                   cyg_uint32 offset);
  73 extern cyg_uint16 cyg_hal_sh_pcic_pci_cfg_read_word  (cyg_uint32 bus, cyg_uint32 devfn,
  74                                                   cyg_uint32 offset);
  75 extern cyg_uint8 cyg_hal_sh_pcic_pci_cfg_read_byte   (cyg_uint32 bus, cyg_uint32 devfn,
  76                                                   cyg_uint32 offset);
  77 extern void cyg_hal_sh_pcic_pci_cfg_write_dword (cyg_uint32 bus, cyg_uint32 devfn,
  78                                              cyg_uint32 offset, cyg_uint32 val);
  79 extern void cyg_hal_sh_pcic_pci_cfg_write_word  (cyg_uint32 bus, cyg_uint32 devfn,
  80                                              cyg_uint32 offset, cyg_uint16 val);
  81 extern void cyg_hal_sh_pcic_pci_cfg_write_byte   (cyg_uint32 bus, cyg_uint32 devfn,
  82                                               cyg_uint32 offset, cyg_uint8 val);
  83
  84 // Initialize the PCI bus.
  85 externC void cyg_hal_sh_pcic_pci_init(void);
  86 #define HAL_PCI_INIT() cyg_hal_sh_pcic_pci_init()
  87
  88 // Map PCI device resources starting from these addresses in PCI space.
  89 // leave gap at start of IO and mem for super IO controller
  90 #define HAL_PCI_ALLOC_BASE_IO     0x00002000
  91 #define HAL_PCI_ALLOC_BASE_MEMORY 0x00000000
  92
  93 // This is where the PCI spaces are mapped in the CPU's address space.
  94 #define HAL_PCI_PHYSICAL_IO_BASE     0  // no direct IO
  95 #define HAL_PCI_PHYSICAL_MEMORY_BASE CYGARC_REG_PCIC_MEM_BASE
  96
  97 // Read a value from the PCI configuration space of the appropriate
  98 // size at an address composed from the bus, devfn and offset.
  99 #define HAL_PCI_CFG_READ_UINT8( __bus, __devfn, __offset, __val )  \
 100     __val = cyg_hal_sh_pcic_pci_cfg_read_byte((__bus),  (__devfn), (__offset))
 101
 102 #define HAL_PCI_CFG_READ_UINT16( __bus, __devfn, __offset, __val ) \
 103     __val = cyg_hal_sh_pcic_pci_cfg_read_word((__bus),  (__devfn), (__offset))
 104
 105 #define HAL_PCI_CFG_READ_UINT32( __bus, __devfn, __offset, __val ) \
 106     __val = cyg_hal_sh_pcic_pci_cfg_read_dword((__bus),  (__devfn), (__offset))
 107
 108 // Write a value to the PCI configuration space of the appropriate
 109 // size at an address composed from the bus, devfn and offset.
 110 #define HAL_PCI_CFG_WRITE_UINT8( __bus, __devfn, __offset, __val )  \
 111     cyg_hal_sh_pcic_pci_cfg_write_byte((__bus),  (__devfn), (__offset), (__val))
 112
 113 #define HAL_PCI_CFG_WRITE_UINT16( __bus, __devfn, __offset, __val ) \
 114     cyg_hal_sh_pcic_pci_cfg_write_word((__bus),  (__devfn), (__offset), (__val))
 115
 116 #define HAL_PCI_CFG_WRITE_UINT32( __bus, __devfn, __offset, __val ) \
 117     cyg_hal_sh_pcic_pci_cfg_write_dword((__bus),  (__devfn), (__offset), (__val))
 118
 119 // Read/write data to PCI IO space
 120 extern void cyg_hal_sh_pcic_pci_io_write_byte (cyg_uint32 addr, cyg_uint8 data);
 121 extern void cyg_hal_sh_pcic_pci_io_write_word (cyg_uint32 addr, cyg_uint16 data);
 122 extern void cyg_hal_sh_pcic_pci_io_write_dword (cyg_uint32 addr, cyg_uint32 data);
 123 extern cyg_uint8 cyg_hal_sh_pcic_pci_io_read_byte (cyg_uint32 addr);
 124 extern cyg_uint16 cyg_hal_sh_pcic_pci_io_read_word (cyg_uint32 addr);
 125 extern cyg_uint32 cyg_hal_sh_pcic_pci_io_read_dword (cyg_uint32 addr);
 126
 127 #define HAL_PCI_IO_READ_UINT8(addr, datum)   datum = cyg_hal_sh_pcic_pci_io_read_byte((cyg_uint32)addr)
 128 #define HAL_PCI_IO_READ_UINT16(addr, datum)  datum = cyg_hal_sh_pcic_pci_io_read_word((cyg_uint32)addr)
 129 #define HAL_PCI_IO_READ_UINT32(addr, datum)  datum = cyg_hal_sh_pcic_pci_io_read_dword((cyg_uint32)addr)
 130 #define HAL_PCI_IO_WRITE_UINT8(addr, datum)  cyg_hal_sh_pcic_pci_io_write_byte((cyg_uint32)addr, datum)
 131 #define HAL_PCI_IO_WRITE_UINT16(addr, datum) cyg_hal_sh_pcic_pci_io_write_word((cyg_uint32)addr, datum)
 132 #define HAL_PCI_IO_WRITE_UINT32(addr, datum) cyg_hal_sh_pcic_pci_io_write_dword((cyg_uint32)addr, datum)
 133
 134 // Translate the PCI interrupt requested by the device (INTA#, INTB#,
 135 // INTC# or INTD#) to the associated CPU interrupt (i.e., HAL vector).
 136 // FIXME: These are incomplete. Not clear from the docs where the
 137 // interrupts are routed - the below makes the onboard PCnet controller
 138 // work.
 139 #define HAL_PCI_TRANSLATE_INTERRUPT( __bus, __devfn, __vec, __valid)          \
 140     CYG_MACRO_START                                                           \
 141     cyg_uint8 __req;                                                          \
 142     HAL_PCI_CFG_READ_UINT8(__bus, __devfn, CYG_PCI_CFG_INT_PIN, __req);       \
 143     if (0 != __req) {                                                         \
 144         CYG_ADDRWORD __translation[4] = {                                     \
 145             CYGNUM_HAL_INTERRUPT_PCID,                                        \
 146             CYGNUM_HAL_INTERRUPT_PCIA,                                        \
 147             CYGNUM_HAL_INTERRUPT_PCIB,                                        \
 148             CYGNUM_HAL_INTERRUPT_PCIC};                                       \
 149                                                                               \
 150         __vec = __translation[((__req+CYG_PCI_DEV_GET_DEV(__devfn))&3)];      \
 151         __valid = true;                                                       \
 152     } else {                                                                  \
 153         /* Device will not generate interrupt requests. */                    \
 154         __valid = false;                                                      \
 155     }                                                                         \
 156     CYG_MACRO_END
 157
 158
 159 #define HAL_PCI_IGNORE_DEVICE(__bus, __dev, __fn)  (0)
 160
 161 // Bus address translation macros
 162 #define HAL_PCI_CPU_TO_BUS(__cpu_addr, __bus_addr)   \
 163     CYG_MACRO_START                                  \
 164     (__bus_addr) = CYGARC_BUS_ADDRESS(__cpu_addr);   \
 165     CYG_MACRO_END
 166
 167 #define HAL_PCI_BUS_TO_CPU(__bus_addr, __cpu_addr)        \
 168     CYG_MACRO_START                                       \
 169     (__cpu_addr) = CYGARC_UNCACHED_ADDRESS(__bus_addr);   \
 170     CYG_MACRO_END
 171
 172 //-----------------------------------------------------------------------------
 173 // end of plf_io.h
 174 #endif // CYGONCE_SH_PLF_IO_H