1 //=============================================================================
5 // BSC (bus state controller) Module register definitions
7 //=============================================================================
8 //####ECOSGPLCOPYRIGHTBEGIN####
9 // -------------------------------------------
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27 // or inline functions from this file, or you compile this file and link it
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38 // -------------------------------------------
39 //####ECOSGPLCOPYRIGHTEND####
40 //=============================================================================
41 //#####DESCRIPTIONBEGIN####
47 //####DESCRIPTIONEND####
49 //=============================================================================
51 //--------------------------------------------------------------------------
52 // Register definitions
53 #define CYGARC_REG_BCR1 0xffffffe0
54 #define CYGARC_REG_BCR2 0xffffffe4
55 #define CYGARC_REG_WCR1 0xffffffe8
56 #define CYGARC_REG_WCR2 0xffffffc0
57 #define CYGARC_REG_WCR3 0xffffffc4
58 #define CYGARC_REG_MCR 0xffffffec
59 #define CYGARC_REG_RTCSR 0xfffffff0
60 #define CYGARC_REG_RTCNT 0xfffffff4
61 #define CYGARC_REG_RTCOR 0xfffffff8
63 #define CYGARC_REG_BSC_WRITE_MAGIC 0xa55a0000
65 #define CYGARC_REG_BCR1_A3LW1 0x00004000
66 #define CYGARC_REG_BCR1_A3LW0 0x00002000
67 #define CYGARC_REG_BCR1_A2ENDIAN 0x00001000 // 0 = big, 1 = little
68 #define CYGARC_REG_BCR1_BSTROM 0x00000800
69 #define CYGARC_REG_BCR1_AHLW1 0x00000200
70 #define CYGARC_REG_BCR1_AHLW0 0x00000100
71 #define CYGARC_REG_BCR1_A1LW1 0x00000080
72 #define CYGARC_REG_BCR1_A1LW0 0x00000040
73 #define CYGARC_REG_BCR1_A0LW1 0x00000020
74 #define CYGARC_REG_BCR1_A0LW0 0x00000010
75 #define CYGARC_REG_BCR1_A4ENDIAN 0x00000008 // 0 = big, 1 = little
76 #define CYGARC_REG_BCR1_DRAM2 0x00000004
77 #define CYGARC_REG_BCR1_DRAM1 0x00000002
78 #define CYGARC_REG_BCR1_DRAM0 0x00000001
80 // Bus widths for areas
81 #define CYGARC_REG_BCR2_A4_8 0x00000100
82 #define CYGARC_REG_BCR2_A4_16 0x00000200
83 #define CYGARC_REG_BCR2_A4_32 0x00000300
84 #define CYGARC_REG_BCR2_A3_8 0x00000040
85 #define CYGARC_REG_BCR2_A3_16 0x00000080
86 #define CYGARC_REG_BCR2_A3_32 0x000000c0
87 #define CYGARC_REG_BCR2_A2_8 0x00000010
88 #define CYGARC_REG_BCR2_A2_16 0x00000020
89 #define CYGARC_REG_BCR2_A2_32 0x00000030
90 #define CYGARC_REG_BCR2_A1_8 0x00000004
91 #define CYGARC_REG_BCR2_A1_16 0x00000008
92 #define CYGARC_REG_BCR2_A1_32 0x0000000c
94 // Intercycle wait states
95 #define CYGARC_REG_WCR1_A3WI_MASK 0x0000c000 // Intercycle Idle Specification
96 #define CYGARC_REG_WCR1_A3WI_SHIFT 14
97 #define CYGARC_REG_WCR1_A2WI_MASK 0x00003000
98 #define CYGARC_REG_WCR1_A2WI_SHIFT 12
99 #define CYGARC_REG_WCR1_A1WI_MASK 0x00000c00
100 #define CYGARC_REG_WCR1_A1WI_SHIFT 10
101 #define CYGARC_REG_WCR1_A0WI_MASK 0x00000300
102 #define CYGARC_REG_WCR1_A0WI_SHIFT 8
103 #define CYGARC_REG_WCR1_A3W_MASK 0x000000c0 // waits
104 #define CYGARC_REG_WCR1_A3W_SHIFT 6
105 #define CYGARC_REG_WCR1_A2W_MASK 0x00000030
106 #define CYGARC_REG_WCR1_A2W_SHIFT 4
107 #define CYGARC_REG_WCR1_A1W_MASK 0x0000000c
108 #define CYGARC_REG_WCR1_A1W_SHIFT 2
109 #define CYGARC_REG_WCR1_A0W_MASK 0x00000003
110 #define CYGARC_REG_WCR1_A0W_SHIFT 0
112 #define CYGARC_REG_WCR1_WI_0 0
113 #define CYGARC_REG_WCR1_WI_1 1
114 #define CYGARC_REG_WCR1_WI_2 2
115 #define CYGARC_REG_WCR1_WI_4 3
117 #define CYGARC_REG_WCR1_W_0 0
118 #define CYGARC_REG_WCR1_W_1 1
119 #define CYGARC_REG_WCR1_W_2 2
120 #define CYGARC_REG_WCR1_W_LONG 3
124 #define CYGARC_REG_WCR2_A4WD_MASK 0x0000c000 // External waits for A4
125 #define CYGARC_REG_WCR2_A4WD_SHIFT 14
126 #define CYGARC_REG_WCR2_A4WM 0x00001000 // external wait mask
127 #define CYGARC_REG_WCR2_A3WM 0x00000800 // external wait mask
128 #define CYGARC_REG_WCR2_A2WM 0x00000400 // external wait mask
129 #define CYGARC_REG_WCR2_A1WM 0x00000200 // external wait mask
130 #define CYGARC_REG_WCR2_A0WM 0x00000100 // external wait mask
131 #define CYGARC_REG_WCR2_A4WI_MASK 0x0000000c // Intercycle Wait states
132 #define CYGARC_REG_WCR2_A4WI_SHIFT 2
133 #define CYGARC_REG_WCR2_A4W_MASK 0x00000003 // Wait states
134 #define CYGARC_REG_WCR2_A4W_SHIFT 0
136 #define CYGARC_REG_WCR2_A4WD_0WS 0
137 #define CYGARC_REG_WCR2_A4WD_1WS 1
138 #define CYGARC_REG_WCR2_A4WD_4WS 2
141 //--------------------------------------------------------------------------
142 // Additional type definitions
143 #if (CYGARC_SH_MOD_BCN > 1)
144 #define CYGARC_REG_BCR3 0xfffffffc
149 //-----------------------------------------------------------------------------
150 // Calculate constants needed to drive the proper SDRAM refresh rate. Argument
151 // is delay between required refresh events in microseconds (us). Should be
152 // available off the SDRAM spec sheet.
153 // These should be a part of a fully CDLicized memory controller setup.
154 #define CYGARC_RTCSR_PRESCALE(_r_) \
155 (((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(4*1000000))<256) ? 4 : \
156 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(16*1000000))<256) ? 16 : \
157 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(64*1000000))<256) ? 64 : \
158 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(256*1000000))<256) ? 256 : \
159 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(1024*1000000))<256) ? 1024 : \
160 ((CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(2048*1000000))<256) ? 2048 : 4096)
162 // These two macros provide the static values we need to stuff into the
164 #define CYGARC_RTCSR_CKSx(_r_) \
165 (( 4 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x08 : \
166 ( 16 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x10 : \
167 ( 64 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x18 : \
168 ( 256 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x20 : \
169 (1024 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x28 : \
170 (2048 == CYGARC_RTCSR_PRESCALE(_r_)) ? 0x30 : 0x38 )
172 #define CYGARC_RTCSR_N(_r_) \
173 (CYGHWR_HAL_SH_BOARD_SPEED*(_r_)/(CYGARC_RTCSR_PRESCALE(_r_)*1000000))