1 #ifndef CYGONCE_VAR_CACHE_H
2 #define CYGONCE_VAR_CACHE_H
4 //=============================================================================
8 // HAL variant cache control API
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
17 // the terms of the GNU General Public License as published by the Free
18 // Software Foundation; either version 2 or (at your option) any later version.
20 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
25 // You should have received a copy of the GNU General Public License along
26 // with eCos; if not, write to the Free Software Foundation, Inc.,
27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
29 // As a special exception, if other files instantiate templates or use macros
30 // or inline functions from this file, or you compile this file and link it
31 // with other works to produce a work based on this file, this file does not
32 // by itself cause the resulting work to be covered by the GNU General Public
33 // License. However the source code for this file must still be made available
34 // in accordance with section (3) of the GNU General Public License.
36 // This exception does not invalidate any other reasons why a work based on
37 // this file might be covered by the GNU General Public License.
39 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
49 // Purpose: Cache control API
50 // Description: The macros defined here provide the HAL APIs for handling
51 // cache control operations.
53 // #include <cyg/hal/hal_cache.h>
57 //####DESCRIPTIONEND####
59 //=============================================================================
61 #include <pkgconf/system.h>
62 #include <pkgconf/hal.h>
63 #include <cyg/infra/cyg_type.h>
64 #include <cyg/hal/hal_io.h> // HAL_READ/WRITE macros
66 #include <cyg/hal/plf_cache.h> // Platform cache definitions
68 #include CYGBLD_HAL_CPU_MODULES_H // cache module specs
70 #include <cyg/hal/sh_regs.h> // CYGARC_REG_ definitions
72 //-----------------------------------------------------------------------------
73 // Cache dimensions - one unified cache
75 #define HAL_CACHE_UNIFIED
77 #define HAL_UCACHE_SIZE CYGARC_SH_MOD_CAC_SIZE
78 #define HAL_UCACHE_LINE_SIZE CYGARC_SH_MOD_CAC_LINE_SIZE
79 #define HAL_UCACHE_WAYS CYGARC_SH_MOD_CAC_WAYS
81 #define HAL_UCACHE_SETS (HAL_UCACHE_SIZE/(HAL_UCACHE_LINE_SIZE*HAL_UCACHE_WAYS))
83 //-----------------------------------------------------------------------------
84 // Global control of cache
86 // This is all handled in assembly (see variant.S) due to a requirement about
87 // not fiddling the cache from cachable memory.
89 externC void cyg_hal_cache_enable(void);
90 externC void cyg_hal_cache_disable(void);
91 externC void cyg_hal_cache_invalidate_all(void);
92 externC void cyg_hal_cache_sync(void);
93 externC void cyg_hal_cache_write_mode(int mode);
96 #define HAL_UCACHE_ENABLE() cyg_hal_cache_enable()
99 #define HAL_UCACHE_DISABLE() cyg_hal_cache_disable()
101 #if (CYGARC_SH_MOD_CAC == 1)
102 // Invalidate the entire cache
103 #define HAL_UCACHE_INVALIDATE_ALL() cyg_hal_cache_invalidate_all()
105 // Synchronize the contents of the cache with memory.
106 #define HAL_UCACHE_SYNC() cyg_hal_cache_sync()
108 // Query the state of the cache (does not affect the caching)
109 #define HAL_UCACHE_IS_ENABLED(_state_) \
112 HAL_READ_UINT8(CYGARC_REG_CCR, _tmp); \
113 (_state_) = (_tmp & CYGARC_REG_CCR_CE) ? 1 : 0; \
116 // Set the cache refill burst size
117 //#define HAL_UCACHE_BURST_SIZE(_size_)
119 // Set the cache write mode
120 #define HAL_UCACHE_WRITE_MODE( _mode_ ) \
123 if (HAL_UCACHE_WRITETHRU_MODE == _mode_) \
126 _m_ = CYGARC_REG_CCR_WB; \
127 cyg_hal_cache_write_mode(_m_); \
130 #define HAL_UCACHE_WRITETHRU_MODE 0
131 #define HAL_UCACHE_WRITEBACK_MODE 1
133 #elif (CYGARC_SH_MOD_CAC == 2)
135 // Invalidate the entire cache
136 #define HAL_UCACHE_INVALIDATE_ALL() \
139 HAL_UCACHE_IS_ENABLED(was_enabled); \
140 cyg_hal_cache_disable(); \
141 cyg_hal_cache_invalidate_all(); \
142 if (was_enabled) cyg_hal_cache_enable(); \
145 // Synchronize the contents of the cache with memory.
146 #define HAL_UCACHE_SYNC() HAL_UCACHE_INVALIDATE_ALL()
148 // Query the state of the cache (does not affect the caching)
149 #define HAL_UCACHE_IS_ENABLED(_state_) \
152 HAL_READ_UINT16(CYGARC_REG_CCR, _tmp); \
153 (_state_) = (_tmp & CYGARC_REG_CCR_CE) ? 1 : 0; \
157 # error "No cache operators for INTC type"
160 // Load the contents of the given address range into the cache
161 // and then lock the cache so that it stays there.
162 //#define HAL_UCACHE_LOCK(_base_, _size_)
164 // Undo a previous lock operation
165 //#define HAL_UCACHE_UNLOCK(_base_, _size_)
167 // Unlock entire cache
168 //#define HAL_UCACHE_UNLOCK_ALL()
170 //-----------------------------------------------------------------------------
171 // Cache line control
173 // Allocate cache lines for the given address range without reading its
174 // contents from memory.
175 //#define HAL_UCACHE_ALLOCATE( _base_ , _size_ )
177 // Write dirty cache lines to memory and invalidate the cache entries
178 // for the given address range.
179 //#define HAL_UCACHE_FLUSH( _base_ , _size_ )
181 // Invalidate cache lines in the given range without writing to memory.
182 //#define HAL_UCACHE_INVALIDATE( _base_ , _size_ )
184 // Write dirty cache lines to memory for the given address range.
185 //#define HAL_UCACHE_STORE( _base_ , _size_ )
188 // Preread the given range into the cache with the intention of reading
190 //#define HAL_UCACHE_READ_HINT( _base_ , _size_ )
192 // Preread the given range into the cache with the intention of writing
194 //#define HAL_UCACHE_WRITE_HINT( _base_ , _size_ )
196 // Allocate and zero the cache lines associated with the given range.
197 //#define HAL_UCACHE_ZERO( _base_ , _size_ )
200 //-----------------------------------------------------------------------------
201 // Data and instruction cache macros map onto the both-cache macros
203 //-----------------------------------------------------------------------------
204 // Global control of data cache
206 #define HAL_DCACHE_SIZE HAL_UCACHE_SIZE
207 #define HAL_DCACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
208 #define HAL_DCACHE_WAYS HAL_UCACHE_WAYS
209 #define HAL_DCACHE_SETS HAL_UCACHE_SETS
211 // Enable the data cache
212 #define HAL_DCACHE_ENABLE() HAL_UCACHE_ENABLE()
214 // Disable the data cache
215 #define HAL_DCACHE_DISABLE() HAL_UCACHE_DISABLE()
217 // Invalidate the entire cache
218 #define HAL_DCACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
220 // Synchronize the contents of the cache with memory.
221 #define HAL_DCACHE_SYNC() HAL_UCACHE_SYNC()
223 // Query the state of the data cache
224 #define HAL_DCACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
226 // Set the data cache refill burst size
227 //#define HAL_DCACHE_BURST_SIZE(_size_)
229 // Set the data cache write mode
230 //#define HAL_DCACHE_WRITE_MODE( _mode_ )
232 //#define HAL_DCACHE_WRITETHRU_MODE 0
233 //#define HAL_DCACHE_WRITEBACK_MODE 1
235 // Load the contents of the given address range into the data cache
236 // and then lock the cache so that it stays there.
237 //#define HAL_DCACHE_LOCK(_base_, _size_)
239 // Undo a previous lock operation
240 //#define HAL_DCACHE_UNLOCK(_base_, _size_)
242 // Unlock entire cache
243 //#define HAL_DCACHE_UNLOCK_ALL()
245 //-----------------------------------------------------------------------------
246 // Data cache line control
248 // Allocate cache lines for the given address range without reading its
249 // contents from memory.
250 //#define HAL_DCACHE_ALLOCATE( _base_ , _size_ )
252 // Write dirty cache lines to memory and invalidate the cache entries
253 // for the given address range.
254 #define HAL_DCACHE_FLUSH( _base_ , _size_ ) HAL_UCACHE_FLUSH( _base_, _size_ )
256 // Invalidate cache lines in the given range without writing to memory.
257 //#define HAL_DCACHE_INVALIDATE( _base_ , _size_ )
259 // Write dirty cache lines to memory for the given address range.
260 //#define HAL_DCACHE_STORE( _base_ , _size_ )
262 // Preread the given range into the cache with the intention of reading
264 //#define HAL_DCACHE_READ_HINT( _base_ , _size_ )
266 // Preread the given range into the cache with the intention of writing
268 //#define HAL_DCACHE_WRITE_HINT( _base_ , _size_ )
270 // Allocate and zero the cache lines associated with the given range.
271 //#define HAL_DCACHE_ZERO( _base_ , _size_ )
273 //-----------------------------------------------------------------------------
274 // Global control of Instruction cache
276 #define HAL_ICACHE_SIZE HAL_UCACHE_SIZE
277 #define HAL_ICACHE_LINE_SIZE HAL_UCACHE_LINE_SIZE
278 #define HAL_ICACHE_WAYS HAL_UCACHE_WAYS
279 #define HAL_ICACHE_SETS HAL_UCACHE_SETS
281 // Enable the instruction cache
282 #define HAL_ICACHE_ENABLE() HAL_UCACHE_ENABLE()
284 // Disable the instruction cache
285 #define HAL_ICACHE_DISABLE() HAL_UCACHE_DISABLE()
287 // Invalidate the entire cache
288 #define HAL_ICACHE_INVALIDATE_ALL() HAL_UCACHE_INVALIDATE_ALL()
291 // Synchronize the contents of the cache with memory.
292 #define HAL_ICACHE_SYNC() HAL_UCACHE_SYNC()
294 // Query the state of the instruction cache
295 #define HAL_ICACHE_IS_ENABLED(_state_) HAL_UCACHE_IS_ENABLED(_state_)
297 // Set the instruction cache refill burst size
298 //#define HAL_ICACHE_BURST_SIZE(_size_)
300 // Load the contents of the given address range into the instruction cache
301 // and then lock the cache so that it stays there.
303 //#define HAL_ICACHE_LOCK(_base_, _size_)
305 // Undo a previous lock operation
306 //#define HAL_ICACHE_UNLOCK(_base_, _size_)
308 // Unlock entire cache
309 //#define HAL_ICACHE_UNLOCK_ALL()
311 //-----------------------------------------------------------------------------
312 // Instruction cache line control
314 // Invalidate cache lines in the given range without writing to memory.
315 //#define HAL_ICACHE_INVALIDATE( _base_ , _size_ )
317 //-----------------------------------------------------------------------------
318 #endif // ifndef CYGONCE_VAR_CACHE_H
319 // End of var_cache.h