1 #ifndef CYGONCE_HAL_VARIANT_INC
2 #define CYGONCE_HAL_VARIANT_INC
3 ##=============================================================================
7 ## SH2 variant assembler header file
9 ##=============================================================================
10 #####ECOSGPLCOPYRIGHTBEGIN####
11 ## -------------------------------------------
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40 ## -------------------------------------------
41 #####ECOSGPLCOPYRIGHTEND####
42 ##=============================================================================
43 #######DESCRIPTIONBEGIN####
48 ## Purpose: SH2 variant definitions and init code
49 ## Description: This file contains various definitions and macros that are
50 ## useful for writing assembly code for the SH2 CPU family.
52 ## #include <cyg/hal/variant.inc>
56 ######DESCRIPTIONEND####
58 ##=============================================================================
60 #include <pkgconf/hal.h>
61 #include <cyg/hal/sh_regs.h>
63 #===========================================================================
64 ## SR initialization value
65 ## zero all bits except:
66 ## I0-3 = Mask out all interrupts but NMI.
68 #define CYG_SR (CYGARC_REG_SR_IMASK)
70 ##-----------------------------------------------------------------------------
71 ## Hardware init macros
72 #ifndef CYGPKG_HAL_SH_POST_RESET_INIT
73 .macro hal_post_reset_init
75 mov.l $nCYG_SR,r1 ! Put CPU in a well-known state
78 mov.l $CYGARC_REG_CCR,r1 ! Disable cache
79 #if (CYGARC_SH_MOD_CAC == 1)
81 #elif (CYGARC_SH_MOD_CAC == 2)
84 # error "No CAC clear code"
86 #ifdef CYGARC_SH_MOD_UBC
87 #if (CYGARC_SH_MOD_UBC == 2)
88 mov.l $CYGARC_REG_BBRA,r1 ! Disable UBC Channel A
90 mov.l $CYGARC_REG_BBRB,r1 ! Disable UBC Channel B
92 mov.l $CYGARC_REG_BBRC,r1 ! Disable UBC Channel C
94 mov.l $CYGARC_REG_BBRD,r1 ! Disable UBC Channel D
98 #ifdef CYGARC_SH_MOD_FRT
99 mov.l $CYGARC_REG_TIER,r1 ! Disable FRT interrupts
102 #ifdef CYGARC_SH_MOD_CMT
103 mov.l $CYGARC_REG_CMSTR,r1 ! Disable CMT timers
106 mov.l $CYGARC_REG_IPRA,r1 ! Disable interrupt request sources
108 mov.l $CYGARC_REG_IPRB,r1
110 #if (CYGARC_SH_MOD_INTC == 1)
111 mov.l $CYGARC_REG_IPRC,r1
113 mov.l $CYGARC_REG_IPRD,r1
115 mov.l $CYGARC_REG_IPRE,r1
117 mov.w $nCYG_ICR_INIT,r0
118 mov.l $CYGARC_REG_ICR,r1 ! Set interrupt controller mode
120 #elif (CYGARC_SH_MOD_INTC == 2)
121 mov.l $CYGARC_REG_IPRC,r1
123 mov.l $CYGARC_REG_IPRD,r1
125 mov.l $CYGARC_REG_IPRE,r1
127 mov.l $CYGARC_REG_IPRF,r1
129 mov.l $CYGARC_REG_IPRG,r1
131 mov.l $CYGARC_REG_IPRH,r1
133 mov.l $CYGARC_REG_ICR,r1 ! level triggered
135 mov.l $CYGARC_REG_ISR,r1 ! Clear any flags
138 # error "No INTC clear code"
140 mov.w $nCYG_WTCSR_INIT,r0 ! Disable watchdog
141 mov.l $CYGARC_REG_WTCSR_W,r1
144 # Initialize VBR if necessary
145 #if !defined(CYG_HAL_STARTUP_RAM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
146 mov.l $_HW_EXC_ENTRY_TABLE,r1 ! Set VBR
153 .word CYGARC_REG_WTCSR_INIT ! clear all CSR bits
161 .long CYGARC_REG_BBRA
163 .long CYGARC_REG_BBRB
165 .long CYGARC_REG_BBRC
167 .long CYGARC_REG_BBRD
168 #ifdef CYGARC_SH_MOD_FRT
170 .long CYGARC_REG_TIER
172 #ifdef CYGARC_SH_MOD_CMT
174 .long CYGARC_REG_CMSTR
177 .long CYGARC_REG_WTCSR_W
178 #if !defined(CYG_HAL_STARTUP_RAM) || !defined(CYGSEM_HAL_USE_ROM_MONITOR)
179 SYM_PTR_REF(_HW_EXC_ENTRY_TABLE)
182 .long CYGARC_REG_IPRA
184 .long CYGARC_REG_IPRB
185 #if (CYGARC_SH_MOD_INTC == 1)
187 .long CYGARC_REG_IPRC
189 .long CYGARC_REG_IPRD
191 .long CYGARC_REG_IPRE
195 .word CYGARC_REG_ICR_INIT
196 #elif (CYGARC_SH_MOD_INTC == 2)
198 .long CYGARC_REG_IPRC
200 .long CYGARC_REG_IPRD
202 .long CYGARC_REG_IPRE
204 .long CYGARC_REG_IPRF
206 .long CYGARC_REG_IPRG
208 .long CYGARC_REG_IPRH
217 #define CYGPKG_HAL_SH_POST_RESET_INIT
220 ##-----------------------------------------------------------------------------
221 ## Interrupt decode macros
222 .macro hal_intc_decode tmp,inum
225 #ifdef CYGIMP_HAL_COMMON_INTERRUPTS_CHAIN
226 .macro hal_intc_translate inum,vnum
227 mov #0,\vnum ! Just vector zero is supported
230 .macro hal_intc_translate inum,vnum
231 mov \inum,\vnum ! Vector == interrupt number
232 shll2 \vnum ! get from vector number to ISR index
236 #------------------------------------------------------------------------------
237 #endif // CYGONCE_HAL_VARIANT_INC