packages/hal/sh/sh2/v2_0/src/sh2_scif.c

   1 //=============================================================================
   2 //
   3 //      sh2_scif.c
   4 //
   5 //      Simple driver for the SH2 Serial Communication Interface with FIFO
   6 //
   7 //=============================================================================
   8 //####ECOSGPLCOPYRIGHTBEGIN####
   9 // -------------------------------------------
  10 // This file is part of eCos, the Embedded Configurable Operating System.
  11 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
  12 //
  13 // eCos is free software; you can redistribute it and/or modify it under
  14 // the terms of the GNU General Public License as published by the Free
  15 // Software Foundation; either version 2 or (at your option) any later version.
  16 //
  17 // eCos is distributed in the hope that it will be useful, but WITHOUT ANY
  18 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
  19 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  20 // for more details.
  21 //
  22 // You should have received a copy of the GNU General Public License along
  23 // with eCos; if not, write to the Free Software Foundation, Inc.,
  24 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  25 //
  26 // As a special exception, if other files instantiate templates or use macros
  27 // or inline functions from this file, or you compile this file and link it
  28 // with other works to produce a work based on this file, this file does not
  29 // by itself cause the resulting work to be covered by the GNU General Public
  30 // License. However the source code for this file must still be made available
  31 // in accordance with section (3) of the GNU General Public License.
  32 //
  33 // This exception does not invalidate any other reasons why a work based on
  34 // this file might be covered by the GNU General Public License.
  35 //
  36 // Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
  37 // at http://sources.redhat.com/ecos/ecos-license/
  38 // -------------------------------------------
  39 //####ECOSGPLCOPYRIGHTEND####
  40 //=============================================================================
  41 //#####DESCRIPTIONBEGIN####
  42 //
  43 // Author(s):   jskov
  44 // Contributors:jskov
  45 // Date:        2001-01-16
  46 // Description: Simple driver for the SH Serial Communication Interface
  47 //              The driver can be used for either the SCIF or the IRDA
  48 //              modules (the latter can act as the former).
  49 //              Clients of this file can configure the behavior with:
  50 //              CYGNUM_SCIF_PORTS: number of SCI ports
  51 //
  52 // Note:        It should be possible to configure a channel to IRDA mode.
  53 //              Worry about that when some board needs it.
  54 //
  55 //####DESCRIPTIONEND####
  56 //
  57 //=============================================================================
  58
  59 #include <pkgconf/hal.h>
  60
  61 #ifdef CYGNUM_HAL_SH_SH2_SCIF_PORTS
  62
  63 #include <cyg/hal/hal_io.h>             // IO macros
  64 #include <cyg/hal/drv_api.h>            // CYG_ISR_HANDLED
  65 #include <cyg/hal/hal_misc.h>           // Helper functions
  66 #include <cyg/hal/hal_intr.h>           // HAL_ENABLE/MASK/UNMASK_INTERRUPTS
  67 #include <cyg/hal/hal_arch.h>           // SAVE/RESTORE GP
  68 #include <cyg/hal/hal_if.h>             // Calling-if API
  69 #include <cyg/hal/sh_regs.h>            // serial register definitions
  70 #include <cyg/hal/sh_stub.h>            // target_register_t
  71
  72 #define CYGPRI_HAL_SH_SH2_SCIF_PRIVATE
  73 #include <cyg/hal/sh2_scif.h>           // our header
  74
  75 //--------------------------------------------------------------------------
  76
  77 void
  78 cyg_hal_plf_scif_init_channel(channel_data_t* chan)
  79 {
  80     cyg_uint8* base = chan->base;
  81     cyg_uint8 tmp;
  82     cyg_uint16 sr;
  83     int baud_rate = CYGNUM_HAL_SH_SH2_SCIF_BAUD_RATE;
  84
  85     // Disable everything.
  86     HAL_WRITE_UINT8(base+_REG_SCSCR, 0);
  87
  88     // Reset FIFO.
  89     HAL_WRITE_UINT8(base+_REG_SCFCR,
  90                     CYGARC_REG_SCIF_SCFCR_TFRST|CYGARC_REG_SCIF_SCFCR_RFRST);
  91     HAL_WRITE_UINT16(base+_REG_SCFER, 0);
  92
  93     // 8-1-no parity. This is also fine for IrDA mode
  94     HAL_WRITE_UINT8(base+_REG_SCSMR, 0);
  95     if (chan->irda_mode)
  96         HAL_WRITE_UINT8(base+_REG_SCIMR, CYGARC_REG_SCIF_SCIMR_IRMOD);
  97     else {
  98         HAL_WRITE_UINT8(base+_REG_SCIMR, 0);
  99     }
 100
 101     // Set speed to CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE
 102     HAL_READ_UINT8(base+_REG_SCSMR, tmp);
 103     tmp &= ~CYGARC_REG_SCIF_SCSMR_CKSx_MASK;
 104     tmp |= CYGARC_SCBRR_CKSx(baud_rate);
 105     HAL_WRITE_UINT8(base+_REG_SCSMR, tmp);
 106     HAL_WRITE_UINT8(base+_REG_SCBRR, CYGARC_SCBRR_N(baud_rate));
 107
 108     // Let things settle: Here we should should wait the equivalent of
 109     // one bit interval,
 110     // i.e. 1/CYGNUM_HAL_SH_SH2_SCIF_DEFAULT_BAUD_RATE second, but
 111     // until we have something like the Linux delay loop, it's hard to
 112     // do reliably. So just move on and hope for the best (this is
 113     // unlikely to cause problems since the CPU has just come out of
 114     // reset anyway).
 115
 116     // Clear status register (read back first).
 117     HAL_READ_UINT16(base+_REG_SCSSR, sr);
 118     HAL_WRITE_UINT16(base+_REG_SCSSR, 0);
 119
 120     HAL_WRITE_UINT8(base+_REG_SC2SSR, CYGARC_REG_SCIF_SC2SSR_BITRATE_16|CYGARC_REG_SCIF_SC2SSR_EI);
 121
 122     // Bring FIFO out of reset and set to trigger on every char in
 123     // FIFO (or C-c input would not be processed).
 124     HAL_WRITE_UINT8(base+_REG_SCFCR,
 125                     CYGARC_REG_SCIF_SCFCR_RTRG_1|CYGARC_REG_SCIF_SCFCR_TTRG_1);
 126
 127     // Leave Tx/Rx interrupts disabled, but enable Rx/Tx (only Rx for IrDA)
 128     if (chan->irda_mode)
 129         HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
 130 #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 131     else if (chan->async_rxtx_mode)
 132         HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
 133 #endif
 134     else
 135         HAL_WRITE_UINT8(base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_TE|CYGARC_REG_SCIF_SCSCR_RE);
 136 }
 137
 138 //static
 139 cyg_bool
 140 cyg_hal_plf_scif_getc_nonblock(void* __ch_data, cyg_uint8* ch)
 141 {
 142     cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 143     cyg_uint16 fdr, sr;
 144     cyg_bool res = false;
 145
 146     HAL_READ_UINT16(base+_REG_SCSSR, sr);
 147     if (sr & CYGARC_REG_SCIF_SCSSR_ER) {
 148         cyg_uint8 ssr2;
 149         HAL_WRITE_UINT16(base+_REG_SCFER, 0);
 150         HAL_READ_UINT8(base+_REG_SC2SSR, ssr2);
 151         ssr2 &= ~CYGARC_REG_SCIF_SC2SSR_ORER;
 152         HAL_WRITE_UINT8(base+_REG_SC2SSR, ssr2);
 153         HAL_WRITE_UINT16(base+_REG_SCSSR,
 154                          CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_BRK | CYGARC_REG_SCIF_SCSSR_FER | CYGARC_REG_SCIF_SCSSR_PER));
 155     }
 156
 157
 158     HAL_READ_UINT16(base+_REG_SCFDR, fdr);
 159     if (0 != (fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK)) {
 160
 161         HAL_READ_UINT8(base+_REG_SCFRDR, *ch);
 162
 163         // Clear DR/RDF flags
 164         HAL_READ_UINT16(base+_REG_SCSSR, sr);
 165         HAL_WRITE_UINT16(base+_REG_SCSSR,
 166                          CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF | CYGARC_REG_SCIF_SCSSR_DR));
 167
 168         res = true;
 169     }
 170
 171     return res;
 172 }
 173
 174 cyg_uint8
 175 cyg_hal_plf_scif_getc(void* __ch_data)
 176 {
 177     cyg_uint8 ch;
 178     CYGARC_HAL_SAVE_GP();
 179
 180     while(!cyg_hal_plf_scif_getc_nonblock(__ch_data, &ch));
 181
 182     CYGARC_HAL_RESTORE_GP();
 183     return ch;
 184 }
 185
 186 void
 187 cyg_hal_plf_scif_putc(void* __ch_data, cyg_uint8 c)
 188 {
 189     channel_data_t* chan = (channel_data_t*)__ch_data;
 190     cyg_uint8* base = chan->base;
 191     cyg_uint16 fdr, sr;
 192     cyg_uint8 scscr = 0;
 193     CYGARC_HAL_SAVE_GP();
 194
 195     HAL_READ_UINT8(base+_REG_SCSCR, scscr);
 196     if (chan->irda_mode) {
 197         HAL_WRITE_UINT8(base+_REG_SCSCR, scscr|CYGARC_REG_SCIF_SCSCR_TE);
 198     }
 199 #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 200     if (chan->async_rxtx_mode) {
 201         HAL_WRITE_UINT8(base+_REG_SCSCR, (scscr|CYGARC_REG_SCIF_SCSCR_TE)&~CYGARC_REG_SCIF_SCSCR_RE);
 202     }
 203 #endif
 204
 205     do {
 206         HAL_READ_UINT16(base+_REG_SCFDR, fdr);
 207     } while (((fdr & CYGARC_REG_SCIF_SCFDR_TCOUNT_MASK) >> CYGARC_REG_SCIF_SCFDR_TCOUNT_shift) == 16);
 208
 209     HAL_WRITE_UINT8(base+_REG_SCFTDR, c);
 210
 211     // Clear FIFO-empty/transmit end flags (read back SR first)
 212     HAL_READ_UINT16(base+_REG_SCSSR, sr);
 213     HAL_WRITE_UINT16(base+_REG_SCSSR, CYGARC_REG_SCIF_SCSSR_CLEARMASK
 214                      & ~(CYGARC_REG_SCIF_SCSSR_TDFE | CYGARC_REG_SCIF_SCSSR_TEND ));
 215
 216     // Hang around until all characters have been safely sent.
 217     do {
 218         HAL_READ_UINT16(base+_REG_SCSSR, sr);
 219     } while ((sr & CYGARC_REG_SCIF_SCSSR_TEND) == 0);
 220
 221
 222     if (chan->irda_mode) {
 223 #ifdef CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
 224         // In IrDA mode there will be generated spurious RX events when
 225         // the TX unit is switched on. Eat that character.
 226         cyg_uint8 _junk;
 227         HAL_READ_UINT8(base+_REG_SCFRDR, _junk);
 228
 229         // Clear buffer full flag (read back first)
 230         HAL_READ_UINT16(base+_REG_SCSSR, sr);
 231         HAL_WRITE_UINT16(base+_REG_SCSSR,
 232                          CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~(CYGARC_REG_SCIF_SCSSR_RDF|CYGARC_REG_SCIF_SCSSR_DR));
 233 #endif // CYGHWR_HAL_SH_SH2_SCIF_IRDA_TXRX_COMPENSATION
 234         // Disable transmitter again
 235         HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
 236     }
 237 #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 238     if (chan->async_rxtx_mode) {
 239         // Disable transmitter, enable receiver
 240         HAL_WRITE_UINT8(base+_REG_SCSCR, scscr);
 241     }
 242 #endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 243
 244     CYGARC_HAL_RESTORE_GP();
 245 }
 246
 247
 248 static channel_data_t channels[CYGNUM_HAL_SH_SH2_SCIF_PORTS];
 249
 250 static void
 251 cyg_hal_plf_scif_write(void* __ch_data, const cyg_uint8* __buf,
 252                          cyg_uint32 __len)
 253 {
 254     CYGARC_HAL_SAVE_GP();
 255
 256     while(__len-- > 0)
 257         cyg_hal_plf_scif_putc(__ch_data, *__buf++);
 258
 259     CYGARC_HAL_RESTORE_GP();
 260 }
 261
 262 static void
 263 cyg_hal_plf_scif_read(void* __ch_data, cyg_uint8* __buf, cyg_uint32 __len)
 264 {
 265     CYGARC_HAL_SAVE_GP();
 266
 267     while(__len-- > 0)
 268         *__buf++ = cyg_hal_plf_scif_getc(__ch_data);
 269
 270     CYGARC_HAL_RESTORE_GP();
 271 }
 272
 273 cyg_bool
 274 cyg_hal_plf_scif_getc_timeout(void* __ch_data, cyg_uint8* ch)
 275 {
 276     channel_data_t* chan = (channel_data_t*)__ch_data;
 277     int delay_count;
 278     cyg_bool res;
 279     CYGARC_HAL_SAVE_GP();
 280
 281     delay_count = chan->msec_timeout * 10; // delay in .1 ms steps
 282
 283     for(;;) {
 284         res = cyg_hal_plf_scif_getc_nonblock(__ch_data, ch);
 285         if (res || 0 == delay_count--)
 286             break;
 287
 288         CYGACC_CALL_IF_DELAY_US(100);
 289     }
 290
 291     CYGARC_HAL_RESTORE_GP();
 292     return res;
 293 }
 294
 295 static int
 296 cyg_hal_plf_scif_control(void *__ch_data, __comm_control_cmd_t __func, ...)
 297 {
 298     static int irq_state = 0;
 299     channel_data_t* chan = (channel_data_t*)__ch_data;
 300     cyg_uint8 scr;
 301     int ret = 0;
 302     CYGARC_HAL_SAVE_GP();
 303
 304     switch (__func) {
 305     case __COMMCTL_IRQ_ENABLE:
 306         irq_state = 1;
 307         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 308         HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
 309         scr |= CYGARC_REG_SCIF_SCSCR_RIE;
 310         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
 311         break;
 312     case __COMMCTL_IRQ_DISABLE:
 313         ret = irq_state;
 314         irq_state = 0;
 315         HAL_INTERRUPT_UNMASK(chan->isr_vector);
 316         HAL_READ_UINT8(chan->base+_REG_SCSCR, scr);
 317         scr &= ~CYGARC_REG_SCIF_SCSCR_RIE;
 318         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, scr);
 319         break;
 320     case __COMMCTL_DBG_ISR_VECTOR:
 321         ret = chan->isr_vector;
 322         break;
 323     case __COMMCTL_SET_TIMEOUT:
 324     {
 325         va_list ap;
 326
 327         va_start(ap, __func);
 328
 329         ret = chan->msec_timeout;
 330         chan->msec_timeout = va_arg(ap, cyg_uint32);
 331
 332         va_end(ap);
 333     }
 334     default:
 335         break;
 336     }
 337     CYGARC_HAL_RESTORE_GP();
 338     return ret;
 339 }
 340
 341 static int
 342 cyg_hal_plf_scif_isr(void *__ch_data, int* __ctrlc,
 343                      CYG_ADDRWORD __vector, CYG_ADDRWORD __data)
 344 {
 345     cyg_uint8 c;
 346     cyg_uint16 fdr, sr;
 347     cyg_uint8* base = ((channel_data_t*)__ch_data)->base;
 348     int res = 0;
 349     CYGARC_HAL_SAVE_GP();
 350
 351     *__ctrlc = 0;
 352     HAL_READ_UINT16(base+_REG_SCFDR, fdr);
 353     if ((fdr & CYGARC_REG_SCIF_SCFDR_RCOUNT_MASK) != 0) {
 354         HAL_READ_UINT8(base+_REG_SCFRDR, c);
 355
 356         // Clear buffer full flag (read back first).
 357         HAL_READ_UINT16(base+_REG_SCSSR, sr);
 358         HAL_WRITE_UINT16(base+_REG_SCSSR,
 359                          CYGARC_REG_SCIF_SCSSR_CLEARMASK & ~CYGARC_REG_SCIF_SCSSR_RDF);
 360
 361         if( cyg_hal_is_break( &c , 1 ) )
 362             *__ctrlc = 1;
 363
 364         res = CYG_ISR_HANDLED;
 365     }
 366
 367     CYGARC_HAL_RESTORE_GP();
 368     return res;
 369 }
 370
 371 void
 372 cyg_hal_plf_scif_init(int scif_index, int comm_index,
 373                       int rcv_vect, cyg_uint8* base, bool irda_mode)
 374 {
 375     channel_data_t* chan = &channels[scif_index];
 376     hal_virtual_comm_table_t* comm;
 377     int cur = CYGACC_CALL_IF_SET_CONSOLE_COMM(CYGNUM_CALL_IF_SET_COMM_ID_QUERY_CURRENT);
 378
 379     // Initialize channel table
 380     chan->base = base;
 381     chan->isr_vector = rcv_vect;
 382     chan->msec_timeout = 1000;
 383     chan->irda_mode = irda_mode;
 384 #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 385     chan->async_rxtx_mode = false;
 386 #endif
 387
 388     // Disable interrupts.
 389     HAL_INTERRUPT_MASK(chan->isr_vector);
 390
 391     // Init channel
 392     cyg_hal_plf_scif_init_channel(chan);
 393
 394     // Setup procs in the vector table
 395
 396     // Initialize channel procs
 397     CYGACC_CALL_IF_SET_CONSOLE_COMM(comm_index);
 398     comm = CYGACC_CALL_IF_CONSOLE_PROCS();
 399     CYGACC_COMM_IF_CH_DATA_SET(*comm, chan);
 400     CYGACC_COMM_IF_WRITE_SET(*comm, cyg_hal_plf_scif_write);
 401     CYGACC_COMM_IF_READ_SET(*comm, cyg_hal_plf_scif_read);
 402     CYGACC_COMM_IF_PUTC_SET(*comm, cyg_hal_plf_scif_putc);
 403     CYGACC_COMM_IF_GETC_SET(*comm, cyg_hal_plf_scif_getc);
 404     CYGACC_COMM_IF_CONTROL_SET(*comm, cyg_hal_plf_scif_control);
 405     CYGACC_COMM_IF_DBG_ISR_SET(*comm, cyg_hal_plf_scif_isr);
 406     CYGACC_COMM_IF_GETC_TIMEOUT_SET(*comm, cyg_hal_plf_scif_getc_timeout);
 407
 408     // Restore original console
 409     CYGACC_CALL_IF_SET_CONSOLE_COMM(cur);
 410 }
 411
 412 #ifdef CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 413 void
 414 cyg_hal_plf_scif_sync_rxtx(int scif_index, bool async_rxtx_mode)
 415 {
 416     channel_data_t* chan = &channels[scif_index];
 417     chan->async_rxtx_mode = async_rxtx_mode;
 418     if (async_rxtx_mode)
 419         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE);
 420     else
 421         HAL_WRITE_UINT8(chan->base+_REG_SCSCR, CYGARC_REG_SCIF_SCSCR_RE|CYGARC_REG_SCIF_SCSCR_TE);
 422 }
 423 #endif // CYGHWR_HAL_SH_SH2_SCIF_ASYNC_RXTX
 424
 425 #endif // CYGNUM_HAL_SH_SH2_SCIF_PORTS
 426
 427 //-----------------------------------------------------------------------------
 428 // end of sh2_scif.c