1 ##==========================================================================
5 ## SH2 variant assembly code
7 ##==========================================================================
8 #####ECOSGPLCOPYRIGHTBEGIN####
9 ## -------------------------------------------
10 ## This file is part of eCos, the Embedded Configurable Operating System.
11 ## Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
13 ## eCos is free software; you can redistribute it and/or modify it under
14 ## the terms of the GNU General Public License as published by the Free
15 ## Software Foundation; either version 2 or (at your option) any later version.
17 ## eCos is distributed in the hope that it will be useful, but WITHOUT ANY
18 ## WARRANTY; without even the implied warranty of MERCHANTABILITY or
19 ## FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
22 ## You should have received a copy of the GNU General Public License along
23 ## with eCos; if not, write to the Free Software Foundation, Inc.,
24 ## 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
26 ## As a special exception, if other files instantiate templates or use macros
27 ## or inline functions from this file, or you compile this file and link it
28 ## with other works to produce a work based on this file, this file does not
29 ## by itself cause the resulting work to be covered by the GNU General Public
30 ## License. However the source code for this file must still be made available
31 ## in accordance with section (3) of the GNU General Public License.
33 ## This exception does not invalidate any other reasons why a work based on
34 ## this file might be covered by the GNU General Public License.
36 ## Alternative licenses for eCos may be arranged by contacting Red Hat, Inc.
37 ## at http://sources.redhat.com/ecos/ecos-license/
38 ## -------------------------------------------
39 #####ECOSGPLCOPYRIGHTEND####
40 ##==========================================================================
41 #######DESCRIPTIONBEGIN####
44 ## Contributors: jskov
46 ## Purpose: SH2 misc assembly code
47 ######DESCRIPTIONEND####
49 ##==========================================================================
51 #include <pkgconf/hal.h>
52 #include <pkgconf/hal_sh.h>
54 #include <cyg/hal/sh_regs.h>
55 #include <cyg/hal/sh2_offsets.inc>
57 #include <cyg/hal/arch.inc>
59 #---------------------------------------------------------------------------
61 # These need to be written in assembly to ensure they do not rely on data
62 # in cachable space (i.e., code must use registers exclusively, not the stack).
64 #if (CYGARC_SH_MOD_CAC == 1)
65 # This macro must be used at the top of each cache function. It ensures
66 # that the code gets executed from a shadow region where caching is disabled
68 .macro GOTO_NONCACHED_SHADOW
80 FUNC_START(cyg_hal_cache_enable)
82 mov.l $CYGARC_REG_CCR,r1
84 mov #CYGARC_REG_CCR_CE,r2
91 FUNC_START(cyg_hal_cache_disable)
93 mov.l $CYGARC_REG_CCR,r1
95 mov #CYGARC_REG_CCR_CE,r2
103 # FIXME: Doc sez we need to disable cache before purging - but only to avoid
104 # messing with the instruction fetches. Since they happen via the non-cached
105 # reflection, try to make do without disable/contidional-enable.
106 FUNC_START(cyg_hal_cache_invalidate_all)
107 GOTO_NONCACHED_SHADOW
108 mov.l $CYGARC_REG_CCR,r1
110 mov #CYGARC_REG_CCR_CP,r2
113 nop ! Nothing in the docs suggest we need
114 nop ! nops here, but without them, the
119 # Sync the cache by forcing read-misses twice for each line
120 # (doing it only once could leave dirty data if it happened
121 # to coincided with the "flush" area used)
122 FUNC_START(cyg_hal_cache_sync)
123 GOTO_NONCACHED_SHADOW
124 mov.l $CYGARC_REG_CACHE_ADDRESS_BASE,r1
125 mov.l $CYGARC_REG_CACHE_ADDRESS_TOP,r2
126 mov.l $CYGARC_REG_CACHE_ADDRESS_STEP,r3
131 add r3,r1 ! delay slot!
136 FUNC_START(cyg_hal_cache_write_mode)
137 GOTO_NONCACHED_SHADOW
138 # Mode argument in r4.
139 # Read current state and mask out the caching mode bit
140 mov.l $CYGARC_REG_CCR,r1
142 mov #CYGARC_REG_CCR_WB,r2
146 # Or in the new setting and restore to CCR
154 $CYGARC_REG_CACHE_ADDRESS_BASE:
156 $CYGARC_REG_CACHE_ADDRESS_TOP:
157 .long (HAL_UCACHE_SIZE*2)
158 $CYGARC_REG_CACHE_ADDRESS_STEP:
159 .long HAL_UCACHE_LINE_SIZE
164 .long 0x1fffffff ! mask off top 3 bits
166 .long 0x20000000 ! base of non-cachable memory
168 #elif (CYGARC_SH_MOD_CAC == 2)
170 FUNC_START(cyg_hal_cache_enable)
171 mov.l $CYGARC_REG_CCR,r1
173 mov #CYGARC_REG_CCR_CE,r2
180 FUNC_START(cyg_hal_cache_disable)
181 mov.l $CYGARC_REG_CCR,r1
183 mov #CYGARC_REG_CCR_CE,r2
191 FUNC_START(cyg_hal_cache_invalidate_all)
192 mov.l $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE,r1
193 mov.l $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP,r2
205 $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE:
206 .long CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_BASE
207 $CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP:
208 .long CYGARC_SH_MOD_CAC_CACHE_ADDRESS_ARRAY_TOP
212 # error "No cache operators for INTC type"
216 SYM_DEF(cyg_hal_ILVL_table)
217 # The first entries in the table have static priorities.
228 #ifdef CYGNUM_HAL_INTERRUPT_LVL14
238 # The rest of the table consists of programmable levels, maintained
239 # by the HAL_INTERRUPT_SET_LEVEL macro.
240 # These default to the highest level so that a spurious
241 # interrupt cause the IPL to be suddenly lowered to allow all
242 # interrupts. This should give a better chance at tracking down
244 .rept (CYGNUM_HAL_ISR_MAX- CYGNUM_HAL_INTERRUPT_LVL_MAX)
248 # All interrupts are masked initally. Set to 1 to enable.
249 SYM_DEF(cyg_hal_IMASK_table)
250 .rept (CYGNUM_HAL_ISR_MAX)