1 #ifndef CYGONCE_HAL_SD0001_H
2 #define CYGONCE_HAL_SD0001_H
4 //=============================================================================
8 // SD0001 support chip - used with SH/7729
10 //=============================================================================
11 //####ECOSGPLCOPYRIGHTBEGIN####
12 // -------------------------------------------
13 // This file is part of eCos, the Embedded Configurable Operating System.
14 // Copyright (C) 1998, 1999, 2000, 2001, 2002 Red Hat, Inc.
16 // eCos is free software; you can redistribute it and/or modify it under
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21 // WARRANTY; without even the implied warranty of MERCHANTABILITY or
22 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
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27 // 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
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30 // or inline functions from this file, or you compile this file and link it
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33 // License. However the source code for this file must still be made available
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40 // at http://sources.redhat.com/ecos/ecos-license/
41 // -------------------------------------------
42 //####ECOSGPLCOPYRIGHTEND####
43 //=============================================================================
44 //#####DESCRIPTIONBEGIN####
49 // Purpose: Support chip
50 // Usage: Included from <cyg/hal/sh_regs.h>
53 //####DESCRIPTIONEND####
55 //=============================================================================
57 # define _SD0001_BASE 0xb0000000
60 //-----------------------------------------------------------------------------
61 // System configuration
62 #define CYGARC_REG_SD0001_RESET (_SD0001_BASE + 0x08)
63 #define CYGARC_REG_SD0001_SDRAM (_SD0001_BASE + 0x10)
64 #define CYGARC_REG_SD0001_INT_STS1 (_SD0001_BASE + 0x20)
65 #define CYGARC_REG_SD0001_INT_ENABLE (_SD0001_BASE + 0x24)
66 #define CYGARC_REG_SD0001_INT_STS2 (_SD0001_BASE + 0x28)
67 #define CYGARC_REG_SD0001_PCI_CTL (_SD0001_BASE + 0x50)
69 #define CYGARC_REG_PCI_IO_MEMOFFSET (_SD0001_BASE + 0x58)
70 #define CYGARC_REG_PCI_MEM_MEMOFFSET (_SD0001_BASE + 0x5c)
73 #define CYGARC_REG_PCI_CFG_ADDR (_SD0001_BASE + 0x60)
74 #define CYGARC_REG_PCI_CFG_DATA (_SD0001_BASE + 0x64)
75 #define CYGARC_REG_PCI_CFG_CMD (_SD0001_BASE + 0x68)
76 #define CYGARC_REG_PCI_CFG_FLG (_SD0001_BASE + 0x6c)
78 #define CYGARC_REG_PCI_CFG_ADDR_ENABLE 0x80000000
79 #define CYGARC_REG_PCI_CFG_ADDR_BUSNO_shift 16
80 #define CYGARC_REG_PCI_CFG_ADDR_FUNC_shift 8
82 #define CYGARC_REG_PCI_CFG_CMD_BE3 0x00080000
83 #define CYGARC_REG_PCI_CFG_CMD_BE2 0x00040000
84 #define CYGARC_REG_PCI_CFG_CMD_BE1 0x00020000
85 #define CYGARC_REG_PCI_CFG_CMD_BE0 0x00010000
87 #define CYGARC_REG_PCI_CFG_CMD_CMDEN 0x00008000
89 #define CYGARC_REG_PCI_CFG_CMD_IO_WRITE 0x00000300
90 #define CYGARC_REG_PCI_CFG_CMD_IO_READ 0x00000200
92 #define CYGARC_REG_PCI_CFG_CMD_WT 0x00000008
93 #define CYGARC_REG_PCI_CFG_CMD_RD 0x00000004
94 #define CYGARC_REG_PCI_CFG_CMD_CFWT 0x00000002
95 #define CYGARC_REG_PCI_CFG_CMD_CFRD 0x00000001
98 #define CYGARC_REG_PCI_CFG_CMD_WCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFWT)
99 #define CYGARC_REG_PCI_CFG_CMD_RCFG (CYGARC_REG_PCI_CFG_CMD_BE3|CYGARC_REG_PCI_CFG_CMD_BE2|CYGARC_REG_PCI_CFG_CMD_BE1|CYGARC_REG_PCI_CFG_CMD_BE0|CYGARC_REG_PCI_CFG_CMD_CFRD)
103 #define CYGARC_REG_SD0001_PCI_CTL_ENDIAN2 0x40000000
104 #define CYGARC_REG_SD0001_PCI_CTL_MAX_DEADLOCK_CNT 0x0000ff00
105 #define CYGARC_REG_SD0001_PCI_CTL_MAX_RETRY_CNT 0x000000f0
108 #define CYGARC_REG_PCI_CFG_FLG_ACTIVE 0x00000001
111 #define CYGARC_REG_SD0001_RESET_SWRST 0x80000000
112 #define CYGARC_REG_SD0001_RESET_PCIRST 0x40000000
115 #define CYGARC_REG_SD0001_SDRAM_SDKIND_128M 0x80000000
116 #define CYGARC_REG_SD0001_SDRAM_SDSIZE_8 0x10000000
117 #define CYGARC_REG_SD0001_SDRAM_REF_MUMBLE 0x00008000
118 #define CYGARC_REG_SD0001_SDRAM_LMODE_CAS2 0x00000010
120 #define CYGARC_REG_SD0001_SDRAM_INIT (CYGARC_REG_SD0001_SDRAM_SDKIND_128M\
121 |CYGARC_REG_SD0001_SDRAM_SDSIZE_8\
122 |CYGARC_REG_SD0001_SDRAM_REF_MUMBLE\
123 |CYGARC_REG_SD0001_SDRAM_LMODE_CAS2)
126 #define CYGARC_REG_SD0001_INT_EN 0x80000000
127 #define CYGARC_REG_SD0001_INT_INTD 0x00000008
128 #define CYGARC_REG_SD0001_INT_INTC 0x00000004
129 #define CYGARC_REG_SD0001_INT_INTB 0x00000002
130 #define CYGARC_REG_SD0001_INT_INTA 0x00000001
133 #endif // CYGONCE_HAL_SD0001_H